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| 型號(hào)： | 37C957FR |
| 廠商： | SMSC Corporation |
| 英文描述： | ULTRA I/O CONTROLLER FOR PORTABLE APPLICATIONS |
| 中文描述： | 超的I / O控制器的便攜式應(yīng)用 |
| 文件頁(yè)數(shù)： | 44/328頁(yè) |
| 文件大?。?/td> | 1208K |
| 代理商： | 37C957FR |
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132
DMA TRANSFERS
DMA transfers are always to or from the ecpDFifo, tFifo or CFifo. DMA utilizes the standard PC DMA
services. To use the DMA transfers, the host first sets up the direction and state as in the
programmed I/O case. Then it programs the DMA controller in the host with the desired count and
memory address. Lastly it sets dmaEn to 1 and serviceIntr to 0. The ECP requests DMA transfers
from the host by activating the PDRQ pin. The DMA will empty or fill the FIFO using the appropriate
direction and mode.
When the terminal count in the DMA controller is reached, an interrupt is
generated and serviceIntr is asserted, disabling DMA. In order to prevent possible blocking of refresh
requests dReq shall not be asserted for more than 32 DMA cycles in a row. The FIFO is enabled
directly by asserting nPDACK and addresses need not be valid. PINTR is generated when a TC is
received.
PDRQ must not be asserted for more than 32 DMA cycles in a row. After the 32nd cycle,
PDRQ must be kept unasserted until nPDACK is deasserted for a minimum of 350nsec. (Note: The
only way to properly terminate DMA transfers is with a TC.)
DMA may be disabled in the middle of a transfer by first disabling the host DMA controller. Then
setting serviceIntr to 1, followed by setting dmaEn to 0, and waiting for the FIFO to become empty
or full. Restarting the DMA is accomplished by enabling DMA in the host, setting dmaEn to 1,
followed by setting serviceIntr to 0.
DMA Mode - Transfers from the FIFO to the Host
(Note: In the reverse mode, the peripheral may not continue to fill the FIFO if it runs out of data to
transfer, even if the chip continues to request more data from the peripheral.)
The ECP activates the PDRQ pin whenever there is data in the FIFO. The DMA controller must
respond to the request by reading data from the FIFO. The ECP will deactivate the PDRQ pin when
the FIFO becomes empty or when the TC becomes true (qualified by nPDACK), indicating that no
more data is required. PDRQ goes inactive after nPDACK goes active for the last byte of a data
transfer (or on the active edge of nIOR, on the last byte, if no edge is present on nPDACK). If PDRQ
goes inactive due to the FIFO going empty, then PDRQ is active again as soon as there is one byte in
the FIFO. If PDRQ goes inactive due to the TC, then PDRQ is active again when there is one byte
in the FIFO, and serviceIntr has been re-enabled. (Note: A data underrun may occur if PDRQ is not
removed in time to prevent an unwanted cycle.)
Programmed I/O Mode or Non-DMA Mode
The ECP or parallel port FIFOs may also be operated using interrupt driven programmed I/O.
Software can determine the writeIntrThreshold, readIntrThreshold, and FIFO depth by accessing
the FIFO in Test Mode.
Programmed I/O transfers are to the ecpDFifo at 400H and ecpAFifo at 000H or from the ecpDFifo
located at 400H, or to/from the tFifo at 400H. To use the programmed I/O transfers, the host first
sets up the direction and state, sets dmaEn to 0 and serviceIntr to 0. The ECP requests programmed
I/O transfers from the host by activating the PINTR pin. The programmed I/O will empty or fill the
FIFO using the appropriate direction and mode.
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