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Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
250687-002
Datasheet
3
R
Contents
1.
Overview.................................................................................................................................... 14
1.1.
System Architecture ...................................................................................................... 15
1.2.
Mobile Intel Pentium
4 Processor-M Host Interface.................................................... 15
1.2.1.
System Bus Error Checking........................................................................ 16
1.3.
System Memory Interface ............................................................................................. 16
1.4.
AGP Interface................................................................................................................ 18
1.5.
Hub Interface................................................................................................................. 18
1.6.
MCH-M Clocking ........................................................................................................... 18
1.7.
System Interrupts .......................................................................................................... 19
2.
Signal Description...................................................................................................................... 20
2.1.
Host Interface Signals ................................................................................................... 21
2.2.
DDR Interface................................................................................................................ 23
2.3.
Hub Interface Signals.................................................................................................... 24
2.4.
AGP Interface Signals................................................................................................... 24
2.4.1.
AGP Addressing Signals............................................................................. 24
2.4.2.
AGP Flow Control Signals........................................................................... 25
2.4.3.
AGP Status Signals..................................................................................... 25
2.4.4.
AGP Strobes ............................................................................................... 26
2.4.5.
AGP/PCI Signals-Semantics....................................................................... 27
2.5.
Clocks, Reset, and Miscellaneous ................................................................................ 30
2.6.
Voltage References, PLL Power ................................................................................... 31
2.7.
Pin State Table.............................................................................................................. 31
3.
Register Description................................................................................................................... 36
3.1.
Conceptual Overview of the Platform Configuration Structure...................................... 36
3.2.
Standard PCI Bus Configuration Mechanism................................................................ 36
3.3.
Routing Configuration Accesses................................................................................... 37
3.3.1.
PCI Bus #0 Configuration Mechanism ........................................................ 37
3.3.2.
Primary PCI and Downstream Configuration Mechanism........................... 37
3.3.3.
AGP Configuration Mechanism................................................................... 38
3.4.
MCH-M Register Introduction........................................................................................ 38
3.5.
I/O Mapped Registers ................................................................................................... 39
3.5.1.
CONFIG_ADDRESS – Configuration Address Register............................. 39
3.5.2.
CONFIG_DATA - Configuration Data Register........................................... 41
3.6.
Memory Mapped Register Space.................................................................................. 42
3.6.1.
DRAMWIDTH—DRAM Width Register....................................................... 43
3.6.2.
DQCMDSTR – Strength Control Register for DQ and CMD Signal
Groups ........................................................................................................ 44
3.6.3.
CKESTR – Strength Control Register for CKE Signal Group ..................... 45
3.6.4.
CSBSTR – Strength Control Register for CS# Signal Group...................... 46
3.6.5.
CKSTR – Strength Control Register for CK Signal Group (CK / CK#)........ 47
3.6.6.
RCVENSTR – Strength Control Register for RCVENOUT# Signals........... 48
3.7.
Host-Hub Interface Bridge Device Registers – Device #0............................................. 48
3.7.1.
VID – Vendor Identification Register – Device#0........................................ 51
3.7.2.
DID – Device Identification Register – Device#0......................................... 51
3.7.3.
PCICMD – PCI Command Register – Device #0........................................ 52
3.7.4.
PCISTS – PCI Status Register – Device #0................................................ 53