參數(shù)資料
型號: 82845Mx
廠商: Intel Corp.
英文描述: Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)
中文描述: 英特爾845系列芯片組的手機(jī)82845MP/82845MZ芯片組內(nèi)存控制器中樞移動(婦幼保健米)
文件頁數(shù): 60/157頁
文件大?。?/td> 1407K
代理商: 82845MX
Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
60
Datasheet
250687-002
R
3.7.17.
DRT – DRAM Timing Register – Device #0
Offset:
Default:
Access:
Size:
78-7Bh
00000010h
Read/Write
32 bits
Bit
Description
31:19
Reserved
18:16
DRAM Idle Timer:
This field determines the number of clocks the DRAM controller will remain in the
idle state before it begins precharging all pages.
000
Infinite
001
0
010
8 DRAM clocks
011
16 DRAM clocks
100
64 DRAM clocks
Others:
reserved
15:11
Reserved
10:9
Activate to Precharge delay (tRAS).
This bit controls the number of DRAM clocks for tRAS.
00
7 Clocks
01
6 Clocks
10
5 Clocks
11
Reserved
8:6
Reserved
5:4
CAS# Latency (tCL).
This bit controls the number of DRAM Clocks between when a read command
is sampled by the SDRAMs and when the MCH-M samples read data from the SDRAMs.
00: 2.5
01: 2 Clocks
10: Reserved
11: Reserved
3
Reserved
2
DRAM RAS# to CAS# Delay (tRCD).
This bit controls the number of clocks inserted between a row
activate command and a read or write command to that row.
Encoding tRCD
0: 3 DRAM Clocks (Default)
1: 2 DRAM Clocks
1
Reserved
0
DRAM RAS# Precharge (tRP).
This bit controls the number of clocks that are inserted between a
row precharge command and an activate command to the same row.
Encoding tRP
0: 3 DRAM Clocks(Default)
1: 2 DRAM Clocks
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
82845MZ 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)
82845PE 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)
8284611SM 制造商:Thomas & Betts 功能描述:
828461-2 制造商:TE Connectivity 功能描述:19P CPC STECK-GEH - Bulk
828462-1 制造商:TE Connectivity 功能描述:19P CPC AUFNAHMEGEH - Bulk