參數(shù)資料
型號： 82845Mx
廠商： Intel Corp.
英文描述： Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)
中文描述： 英特爾845系列芯片組的手機82845MP/82845MZ芯片組內(nèi)存控制器中樞移動（婦幼保健米）
文件頁數(shù)： 83/157頁
文件大?。?/td> 1407K
代理商： 82845MX
Intel
82845MP/82845MZ Chipset-Mobile (MCH-M)
250687-002
Datasheet
83
R
3.7.37.
SMICMD – SMI Command Register – Device #0
Address Offset:
Default Value:
Access:
Size:
CC-CDh
0000h
Read/Write, Read Only
16 bits
This register enables various errors to generate an SMI message via the hub interface A.
Note:
An error can generate one and only one error message via the hub interface A. It is software’s
responsibility to make sure that when an SMI error message is enabled for an error condition; SERR and
SCI error messages are disabled for that same error condition.
Bit
Description
15:2
Reserved
1
SMI on Multiple-bit DRAM ECC Error (DMERR):
When this bit is set, the generation of the hub
interface A SMI message is enabled when the MCH-M DRAM controller detects a multiple-bit error.
For systems not supporting ECC this bit must be disabled.
0
SMI on Single-bit ECC Error (DSERR):
When this bit is set, the generation of the hub interface A
SMI message is enabled when the MCH-M DRAM controller detects a single bit error. For systems
that do not support ECC this bit must be disabled.
3.7.38.
SCICMD – SCI Command Register – Device #0
Address Offset:
Default Value:
Access:
Size:
CE-CDh
0000h
Read/Write, Read Only
16 bits
This register enables various errors to generate a SCI message via the hub interface A.
Note:
An error can generate one and only one error message via the hub interface A. It is software’s
responsibility to make sure that when an SCI error message is enabled for an error condition, SERR and
SMI error messages are disabled for that same error condition.
Bit
Description
15:2
Reserved
1
SCI on Multiple-Bit DRAM ECC Error (DMERR):
When this bit is set, the generation of the hub
interface A SCI message is enabled when the MCH-M DRAM controller detects a multiple-bit error.
For systems not supporting ECC this bit must be disabled.
0
SCI on Single-bit ECC Error (DSERR):
When this bit is set, the generation of the hub interface A
SCI message is enabled when the MCH-M DRAM controller detects a single bit error. For systems
that do not support ECC this bit must be disabled.
相關(guān)PDF資料
PDF描述
82845MZ Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)
82845PE 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)
82845GE 82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)
8284A Clock Generator and Driver for 8066, 8088 Processors
8284A-1 Clock Generator and Driver for 8066, 8088 Processors
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
82845MZ 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:Intel 845 Family Chipset-Mobile 82845MP/82845MZ Chipset Memory Controller Hub Mobile (MCH-M)
82845PE 制造商:INTEL 制造商全稱:Intel Corporation 功能描述:82845GE Graphics and Memory Controller Hub (GMCH) and 82845PE Memory Controller Hub (MCH)
8284611SM 制造商:Thomas & Betts 功能描述:
828461-2 制造商:TE Connectivity 功能描述:19P CPC STECK-GEH - Bulk
828462-1 制造商:TE Connectivity 功能描述:19P CPC AUFNAHMEGEH - Bulk
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