Advance Information
82C205
912-1000-024
Page 19
Revision 1.0
5. Register Descriptions
5.1. Revision Register
7
6
5
4
3
2
1
0
Index 00h
Chip Revision (R)
Default = 00h
Chip Revision
5.2. System Control Register
7
6
5
4
3
2
1
0
Index 01h
System Enable (R/W)
Default = 00h
Reserved
Reserved
Reserved
Reserved
Add one clock
for CPU
read/write:
0: Enable
1: Disable
CPU DRAM
Access:
0: Enable
1: Disable
Video Display
Control
0: Disable
1: Enable
Video Capture
Control
0: Disable
1: Enable
Index 02h
Software Reset (R/W)
Default = 00h
These software resets allow the CPU flexibility for debug and power down functions.
The default value is zero and software reset is unnecessary at startup
Reserved
Reserved
Capture
Reset:
0: Normal
1: Reset
Display Reset:
0: Normal
1: Reset
Reserved
Memory
Controller
Reset:
0: Normal
1: Reset
Reserved
Timer Reset:
0: Normal
1: Reset the
timer
5.3. Memory Control Registers
7
6
5
4
3
2
1
0
Index 04h
Capture Start Address - Field 1 (R/W)
Default = 00h
Starting address for Video Capture Field 1 -- Low Byte
Index 05h
Default = 00h
Starting address for Video Capture Field 1 -- Middle Byte
Index 06h
Default = 00h
Reserved
Reserved
Starting address for Video Capture Field 1 -- High Byte
Index 07h
Capture Start Address - Field 2 (R/W)
Default = 00h
Starting address for Video Capture Field 2 -- Low Byte
Index 08h
Default = 00h
Starting address for Video Capture Field 2 -- Middle Byte
Index 09h
Default = 00h
Reserved
Reserved
Starting address for Video Capture Field 2 -- High Byte