參數(shù)資料
型號(hào)： 82C205
英文描述： Consumer IC
中文描述： 消費(fèi)性IC
文件頁(yè)數(shù)： 40/47頁(yè)
文件大?。?/td> 460K
代理商： 82C205
Advance Information
82C205
912-1000-024
Page 36
Revision 1.0
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Index C9h
Hardware Enables (R/W)
Default = 00h
Control of Wake-up and Power Down for Power Conservation in the 82C200.
Master Bias
0: Disable
1: Enable
Reserved (set
to 0)
Reserved
Line Buffer
Power
0: Disable
1: Enable
VCLK2 PLL
Power
0: Disable
1: Enable
MCK PLL
Power
0: Disable
1: Enable
Reserved (set
to 0)
Reserved
Index CAh
Timer (R/W)
Default = FFh
General Purpose Count Down Timer (in units of 10 us) to assist the software power sequencing.
Generates a timer event whenever it reaches zero. Range from 0~5s.
The low byte should be written last, i.e. write the high and mid bytes before the low byte.
Low Byte
Index CBh
Timer (R/W)
Default = FFh
Mid Byte
Index CCh
Timer (R/W)
Default = 07h
Reserved
Reserved
Reserved
Reserved
Reserved
High Byte
The high byte should be written first,
before writing the mid and low bytes
Index CDh - CEh
Reserved
Default = 00h
5.20. CLUT Registers
This is the Color Look Up Table used for the OSD, providing 8 colors available to 16 entries. A global alpha blend
value is defined for all blending in this mode, and a 1-bit value for each entry selects whether or not the blend will
occur.
Transparent, inverted video, and blinking attributes are also supported.
In the CLUT registers D0h - DFh, the Global Blend Enable and attribute bits (bits 5, 1:0) work together as follows:
000: Normal
X01: Inverted Video
010: Blink, no blend
X11: Transparent
100: Blend
110: Blink, blend
7
6
5
4
3
2
1
0
Index CFh
CLUT Register Control (R/W)
Default = 00h
Reserved
Reserved
Enable CLUT
registers
Global blend value
Can be used in place of the Attribute to define a global value for pixel translucency.
Index D0h
CLUT0 (R/W)
Default = 00h
Reserved
Reserved
Global Blend:
0: Disable
1: Enable
Red
Green
Blue
Attribute
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