Advance Information
82C205
912-1000-024
Page 34
Revision 1.0
5.15. Bandwidth Conservation Registers
7
6
5
4
3
2
1
0
Index B0h
OSD FIFO Word Count (R/W)
Default = 00h
Special register for OSD FIFO control, indicating the number of 64-bit words that will be fetched in one line for OSD.
Index B1h
Reserved
Default = 00h
Index B2h
Panel Display FIFO Word Count (R/W)
Default = 00h
Special register for upper display FIFO control, indicating the number of words that will be fetched for the whole panel.
Index B3h
Reserved
Default = 00h
5.16. Interrupt Control Registers
7
6
5
4
3
2
1
0
Index B4h
Interrupt Enable (R/W)
Default = 00h
VGA
Horizontal
Frequency
Change
interrupt:
0: Disable
(default)
1: Enable
Display VBI
start interrupt:
0: Disable
(default)
1: Enable
Display VBI
end interrupt:
0: Disable
(default)
1: Enable
Capture VBI
start interrupt:
0: Disable
(default)
1: Enable
Capture VBI
end interrupt;
0: Disable
(default)
1: Enable
VGA Vertical
Frequency
Change
interrupt:
0: Disable
(default)
1: Enable
Timer
interrupt:
0: Disable
(default)
1: Enable
Reserved
Index B5h
Interrupt Clear (W)
Default = 00h
VGA
Horizontal
Frequency
Change
interrupt clear:
Write 1 to
clear
Display VBI
start interrupt
clear:
Write 1 to
clear
Display VBI
end interrupt
clear:
Write 1 to
clear
Capture VBI
start interrupt
clear:
Write 1 to
clear
Capture VBI
end interrupt
clear:
Write 1 to
clear
VGA Vertical
Frequency
Change
interrupt clear:
Write 1 to
clear
Timer interrupt
clear:
Write 1 to
clear
Reserved
Index B5h
Interrupt Status (R)
Default = 00h
VGA
Horizontal
Frequency
Change event
status
Display VBI
start event
status:
Occurs at
beginning of
display vertical
sync pulse.
Display VBI
end event
status:
Occurs at end
of display
vertical sync
pulse.
Capture VBI
start event
status:
Occurs at
beginning of
capture
vertical sync
pulse.
Capture VBI
end event
status:
Occurs at end
of capture
vertical sync
pulse.
VGA Vertical
Frequency
Change event
status
Timer event
status:
Occurs when
count-down
timer reaches
zero.
Reserved