參數(shù)資料
型號： 82C205
英文描述： Consumer IC
中文描述： 消費(fèi)性IC
文件頁數(shù)： 35/47頁
文件大?。?/td> 460K
代理商： 82C205
Advance Information
82C205
912-1000-024
Revision 1.0
Page 31
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Index 8Ah
Display Vertical Total - Even Frame (R/W)
Default = 00h
Vertical Total for Even Frame (in units of display video lines).
If odd and even frames have the same vertical total,
this register still needs to be programmed.
Low Byte
Index 8Bh
Display Vertical Total - Even Frame (R/W)
Default = 00h
Reserved
Reserved
Reserved
Reserved
High Byte
Index 8Ch
Display Vertical Sync Width (R/W)
Default = 00h
Vertical Sync Width (in units of display video lines)
Low Byte
Index 8Dh
Display Vertical Sync Width (R/W)
Default = 00h
Reserved
Reserved
Reserved
Reserved
High Byte
Index 8Eh
Display Vertical Display Start (R/W)
Default = 00h
Vertical Display Start (in units of display video lines)
Low Byte
Index 8Fh
Display Vertical Display Start (R/W)
Default = 00h
Reserved
Reserved
Reserved
Reserved
High Byte
Index 90h
Display Vertical Display End (R/W)
Default = 00h
Vertical Display End (in units of display video lines)
Low Byte
Index 91h
Display Vertical Display End (R/W)
Default = 00h
Reserved
Reserved
Reserved
Reserved
High Byte
Index 92h
Vertical Sync Signal Offset Control (R/W)
Default = 05h
Defines the delay in units of capture video lines, from the rising edge of
the capture vertical sync to the rising edge of the display vertical sync
Low Byte
Index 93h
Vertical Sync Signal Offset Control (R/W)
Default = 00h
Reserved
Reserved
Reserved
Reserved
High Byte
Index 94h
Bypass Mode HSYNC Offset (R/W)
Default = 06h
Reserved
High Byte
Index 95h
Bypass Mode HSYNC Offset (R/W)
Default = 0Ah
Defines the delay in units of VCLK2 display HSYNC to capture HSYNC in bypass mode.
Low Byte
Index 96h
Reserved
Default = 00h
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