參數(shù)資料
型號： 91C100FDREVB
廠商： SMSC Corporation
英文描述： FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY
中文描述： 宴快速以太網(wǎng)控制器以全雙工能力
文件頁數(shù)： 11/68頁
文件大?。?/td> 423K
代理商： 91C100FDREVB
SMSC DS – LAN91C100FD REV. B
Page 19
Rev. 05/31/2000
BANK SELECT REGISTER
OFFSET
NAME
TYPE
SYMBOL
E
BANK SELECT
REGISTER
READ/WRITE
BSR
HIGH
BYTE
0
1
0
1
0
1
0
1
LOW
BYTE
BS2
BS1
BS0
X
0
BS2, BS1, BS0 Determine the bank presently in use. This register is always accessible and is used to select the
register bank in use.
The upper byte always reads as 33h and can be used to help determine the I/O location of the LAN91C100FD.
The BANK SELECT REGISTER is always accessible regardless of the value of BS0-2.
Note that the bank select register can be accessed as a doubleword at offset Ch, as a word at offset Eh, or as at
offset Fh, however a doubleword write to offset Ch will write the BANK SELECT REGISTER but will not write the
registers Ch and Dh.
BANK 7 has no internal registers other than the BANK SELECT REGISTER itself. On valid cycles where BANK7 is
selected (BS0=BS1=BS2=1), and A3=0, nCSOUT is activated to facilitate implementation of external registers.
Note: BANK7 does not exist in LAN91C9x devices. For backward S/W compatibility BANK7 accesses should be done
if the Revision Control register indicates the device is the LAN91C100FD.
BANK 0
OFFSET
NAME
TYPE
SYMBOL
0
TRANSMIT CONTROL
REGISTER
READ/WRITE
TCR
This register holds bits programmed by the CPU to control some of the protocol transmit options.
HIGH
BYTE
SWFDUP
0
EPH
LOOP
STP
SQET
FDUPLX
MON_
CSN
0
NOCRC
0
LOW
BYTE
PAD_EN
0
FORCOL
LOOP
TXENA
0
SWFDUP - Enables Switched Full Duplex mode. In this mode, transmit state machine is inhibited from recognizing carrier
sense, so deferrals will not occur. Also inhibits collision count, therefore, the collision related status bits in the EPHSR are
not valid (CTR_ROL, LATCOL, SQET, 16COL, MUL COL, and SNGL COL). Uses COL100 as flow control, limiting
backoff and jam to 1 clock each before inter-frame gap, then retry will occur after IFG. If COL100 is active during
preamble, full preamble will be output before jam. When SWFDUP is high, the values of FDUPLX and MON_CSN have no
effect. This bit should be low for non-MII operation.
EPH_LOOP - Internal loopback at the EPH block. Serial data is internally looped back when set. Defaults low. When
EPH_LOOP is high the following transmit outputs are forced inactive: TXD0-TXD3 = 0h, TXEN100 = TXEN = 0, TXD = 1.
The following and external inputs are blocked: CRS=CRS100=0, COL=COL100=0, RX_DV= RX_ER=0.
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