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參數(shù)資料
| 型號(hào)： | 91C100FDREVB |
| 廠商： | SMSC Corporation |
| 英文描述： | FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY |
| 中文描述： | 宴快速以太網(wǎng)控制器以全雙工能力 |
| 文件頁(yè)數(shù)： | 18/68頁(yè) |
| 文件大?。?/td> | 423K |
| 代理商： | 91C100FDREVB |
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SMSC DS – LAN91C100FD REV. B
Rev. 05/31/2000
FULL STEP - This bit is a general purpose output port. Its inverse value drives pin nFSTEP and it is typically connected to
SEL pin of the LAN83C694. It can be used to select the signaling mode for the AUI or as a general purpose non-volatile
configuration pin. Defaults low.
AUI SELECT - This bit is a general purpose output port. Its value drives pin AUISEL and it is typically connected to MODE1
pin of the LAN83C694. It can be used to select AUI vs. 10BASE-T, or as a general purpose non-volatile configuration pin.
Defaults low.
Reserved - Must be 0.
INT SEL1-0 - Used to select one out of four interrupt pins. The three unused interrupts are tristated.
INT SEL1
INT SEL0
INTERRUPT PIN USED
0
1
0
1
0
1
INTR0
INTR1
INTR2
INTR3
BANK 1
OFFSET
NAME
TYPE
SYMBOL
2
BASE ADDRESS REGISTER
READ/WRITE
BAR
This register holds the I/O address decode option chosen for the LAN91C100FD. It is part of the EEPROM saved setup
and is not usually modified during run-time.
HIGH
BYTE
A15
A14
A13
A9
A8
A7
A6
A5
0
1
0
LOW
BYTE
Reserved
1
0
1
A15 - A13 and A9 - A5 - These bits are compared against the I/O address on the bus to determine the IOBASE for the
LAN91C100FD‘s registers. The 64k I/O space is fully decoded by the LAN91C100FD down to a 16 location space,
therefore the unspecified address lines A4, A10, A11 and A12 must be all zeros.
All bits in this register are loaded from the serial EEPROM. The I/O base decode defaults to 300h (namely, the high byte
defaults to 18h).
Reserved - Must be 0.
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