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參數(shù)資料
| 型號(hào)： | 91C100FDREVB |
| 廠商： | SMSC Corporation |
| 英文描述： | FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY |
| 中文描述： | 宴快速以太網(wǎng)控制器以全雙工能力 |
| 文件頁數(shù)： | 44/68頁 |
| 文件大?。?/td> | 423K |
| 代理商： | 91C100FDREVB |
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SMSC DS – LAN91C100FD REV. B
Page 49
Rev. 05/31/2000
Table 3 - VL Local Bus Signal Connections
VL BUS
SIGNAL
LAN91C100
SIGNAL
NOTES
created typically by using nADS delayed by one LCLK.
IRQn
INTR0-INTR3
Typically uses the interrupt lines on the ISA edge connector of VL
bus
D0-D31
32 bit data bus. The bus byte(s) used to access the device are a
function of nBE0-nBE3:
nBE0 nBE1
nBE2
nBE3
0
Double word access
0
1
Low word access
1
0
High word access
0
1
Byte 0 access
1
0
1
Byte 1 access
1
0
1
Byte 2 access
1
0
Byte 3 access
Not used = tri-state on reads, ignored on writes. Note that nBE2
and nBE3 override the value of A1, which is tied low in this
application.
nLDEV
nLDEV is a totem pole output. nLDEV is active on valid decodes of
A15-A4 and AEN=0.
UNUSED PINS
VCC
nRD nWR
GND
A1 nVLBUS
OPEN
nDATACS
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