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參數(shù)資料
| 型號(hào)： | 91C100FDREVB |
| 廠商： | SMSC Corporation |
| 英文描述： | FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY |
| 中文描述： | 宴快速以太網(wǎng)控制器以全雙工能力 |
| 文件頁數(shù)： | 50/68頁 |
| 文件大?。?/td> | 423K |
| 代理商： | 91C100FDREVB |
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SMSC DS – LAN91C100FD REV. B
Page 54
Rev. 05/31/2000
Table 5 - EISA 32 Bit Slave Signal Connections
EISA BUS
SIGNAL
LAN91C100FD
SIGNAL
NOTES
nEX32
nNOWS
(optional
additional logic)
nLDEV
nLDEV is a totem pole output. nLDEV is active on valid decodes
of LAN91C100FD pins A15-A4, and AEN=0. nNOWS is similar
to nLDEV except that it should go inactive on nSTART rising.
nNOWS can be used to request compressed cycles (1.5 BCLK
long, nRD/nWR will be 1/2 BCLK wide).
THE FOLLOWING SIGNALS SUPPORT SLAVE DMA TYPE "C" BURST CYCLES
BCLK
LCLK
EISA Bus Clock. Data transfer clock for DMA bursts.
nDAK<n>
nDATACS
DMA Acknowledge. Active during Slave DMA cycles. Used by
the LAN91C100FD as nDATACS direct access to data path.
nIORC
W/nR
Indicates the direction and timing of the DMA cycles. High
during LAN91C100FD writes, low during LAN91C100FD reads.
nIOWC
nCYCLE
Indicates slave DMA writes.
nEXRDY
nRDYRTN
EISA bus signal indicating whether a slave DMA cycle will take
place on the next BCLK rising edge, or should be postponed.
nRDYRTN is used as an input in the slave DMA mode to bring
in EXRDY.
UNUSED PINS
VCC
nVLBUS
GND
A1
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