參數(shù)資料
型號： 91C100FDREVB
廠商： SMSC Corporation
英文描述： FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY
中文描述： 宴快速以太網(wǎng)控制器以全雙工能力
文件頁數(shù)： 45/68頁
文件大?。?/td> 423K
代理商： 91C100FDREVB
SMSC DS – LAN91C100FD REV. B
Page 5
Rev. 05/31/2000
DESCRIPTION OF PIN FUNCTIONS
PQFP/TQFP
PIN NO.
NAME
SYMBOL
BUFFER
TYPE
DESCRIPTION
148-159
Address
A4-A15
I
Input. Decoded by LAN91C100FD to determine
access to its registers.
145-147
Address
A1-A3
I
Input. Used by LAN91C100FD for internal register
selection.
193
Address
Enable
AEN
I
Input. Used as an address qualifier. Address
decoding is only enabled when AEN is low.
160-163
nByte
Enable
nBE0-
nBE3
I
Input.
Used during LAN91C100FD register
accesses to determine the width of the access and
the register(s) being accessed. nBE0-nBE3 are
ignored when nDATACS is low (burst accesses)
because 32 bit transfers are assumed.
173-170,
168-166,
164, 144,
142-139,
137-135,
133,
131-129,
127, 126,
124, 123,
121, 118,
117,
115-112, 110
Data Bus
D0-D31
I/O24
Bidirectional. 32 bit data bus used to access the
LAN91C100FD’s internal registers. Data bus has
weak internal pullups. Supports direct connection
to the system bus without external buffering. For
16 bit systems, only D0-D15 are used.
182
Reset
RESET
IS
Input. This input is not considered active unless it
is active for at least 100ns to filter narrow glitches.
95
nAddress
Strobe
nADS
IS
Input. For systems that require address latching,
the rising edge of nADS indicates the latching
moment for A1-A15 and AEN. All LAN91C100FD
internal functions of A1-A15, AEN are latched
except for nLDEV decoding.
183
nCycle
nCYCLE
I
Input. This active low signal is used to control
LAN91C100FD EISA burst mode synchronous bus
cycles.
184
Write/
nRead
W/nR
IS
Input. Defines the direction of synchronous cycles.
Write cycles when high, read cycles when low.
181
nVL Bus
Access
nVLBUS
I with
pullup
Input. When low, the LAN91C100FD synchronous
bus interface is configured for VL Bus accesses.
Otherwise, the LAN91C100FD is configured for
EISA DMA burst accesses. Does not affect the
asynchronous bus interface.
105
Local Bus
Clock
LCLK
I
Input.
Used to interface synchronous buses.
Maximum frequency is 50 MHz. Limited to 8.33
MHz for EISA DMA burst mode.
175
Asynchron-
ous Ready
ARDY
OD16
Open drain output. ARDY may be used when
interfacing
asynchronous
buses
to
extend
accesses. Its rising (access completion) edge is
controlled by the XTAL1 clock and, therefore,
asynchronous to the host CPU or bus clock.
106
nSynchron
-
ous Ready
nSRDY
O16
Output.
This output is used when interfacing
synchronous buses and nVLBUS=0 to extend
accesses. This signal remains normally inactive,
and its falling edge indicates completion.
This
signal is synchronous to the bus clock LCLK.
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