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參數(shù)資料
| 型號(hào)： | 91C100FDREVB |
| 廠商： | SMSC Corporation |
| 英文描述： | FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY |
| 中文描述： | 宴快速以太網(wǎng)控制器以全雙工能力 |
| 文件頁(yè)數(shù)： | 27/68頁(yè) |
| 文件大小： | 423K |
| 代理商： | 91C100FDREVB |
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SMSC DS – LAN91C100FD REV. B
Page 33
Rev. 05/31/2000
The TX EMPTY INT ENABLE should only be set after the following steps:
a) a packet is enqueued for transmission
b) the previous empty condition is cleared (acknowledged)
TX INT - Set when at least one packet transmission was completed. The first packet number to be serviced can be read
from the FIFO PORTS register. The TX INT bit is always the logic complement of the TEMPTY bit in the FIFO PORTS
register. After servicing a packet number, its TX INT interrupt is removed by writing the Interrupt Acknowledge Register with
the TX INT bit set.
RCV INT - Set when a receive interrupt is generated. The first packet number to be serviced can be read from the FIFO
PORTS register. The RCV INT bit is always the logic complement of the REMPTY bit in the FIFO PORTS register.
ERCV INT - Early receive interrupt. Set whenever a receive packet is being received, and the number of bytes received
into memory exceeds the value programmed as ERCV THRESHOLD (Bank 3, Offset Ch). ERCV INT stays set until
acknowledged by writing the INTERRUPT ACKNOWLEDGE REGISTER with the ERCV INT bit set.
Note: If the driver uses AUTO RELEASE mode it should enable TX EMPTY INT as well as TX INT. TX EMPTY INT will be
set when the complete sequence of packets is transmitted. TX INT will be set if the sequence stops due to a fatal error on
any of the packets in the sequence.
FIGURE 5 -
INTERRUPT
STRUCTURE
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6
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