參數(shù)資料
型號(hào)： 91C100FDREVB
廠商： SMSC Corporation
英文描述： FEAST FAST ETHERNET CONTROLLER WITH FULL DUPLEX CAPABILITY
中文描述： 宴快速以太網(wǎng)控制器以全雙工能力
文件頁數(shù)： 22/68頁
文件大?。?/td> 423K
代理商： 91C100FDREVB
SMSC DS – LAN91C100FD REV. B
Page 29
Rev. 05/31/2000
Note 2: When using the RESET TX FIFOS command, the CPU is responsible for releasing the memory associated with
outstanding packets, or re-enqueuing them. Packet numbers in the completion FIFO can be read via the FIFO
ports register before issuing the command.
Note 3: MMU commands releasing memory (commands 4 and 5) should only be issued if the corresponding packet
number has memory allocated to it.
COMMAND SEQUENCING
A second allocate command (command 1) should not be issued until the present one has completed. Completion is
determined by reading the FAILED bit of the allocation result register or through the allocation interrupt.
A second release command (commands 4, 5) should not be issued if the previous one is still being processed. The BUSY
bit indicates that a release command is in progress. After issuing command 5, the contents of the PNR should not be
changed until BUSY goes low. After issuing command 4, command 3 should not be issued until BUSY goes low.
BUSY BIT - Readable at bit 0 of the MMU command register address. When set indicates that MMU is still processing a
release command. When clear, MMU has already completed last release command. BUSY and FAILED bits are set upon
the trailing edge of command.
BANK 2
OFFSET
NAME
TYPE
SYMBOL
2
PACKET NUMBER REGISTER
READ/WRITE
PNR
0
PACKET NUMBER AT TX AREA
0
PACKET NUMBER AT TX AREA - The value written into this register determines which packet number is accessible
through the TX area. Some MMU commands use the number stored in this register as the packet number parameter. This
register is cleared by a RESET or a RESET MMU Command.
OFFSET
NAME
TYPE
SYMBOL
3
ALLOCATION RESULT REGISTER
READ ONLY
ARR
This register is updated upon an ALLOCATE MEMORY MMU command.
FAILED
0
ALLOCATED PACKET NUMBER
1
0
FAILED - A zero indicates a successful allocation completion. If the allocation fails the bit is set and only cleared when the
pending allocation is satisfied. Defaults high upon reset and reset MMU command. For polling purposes, the ALLOC_INT
in the Interrupt Status Register should be used because it is synchronized to the read operation. Sequence:
1) Allocate Command
2) Poll ALLOC_INT bit until set
3) Read Allocation Result Register
ALLOCATED PACKET NUMBER - Packet number associated with the last memory allocation request. The value is only
valid if the FAILED bit is clear.
Note: For software compatibility with future versions, the value read from the ARR after an allocation request is intended to
be written into the PNR as is, without masking higher bits (provided FAILED = 0).
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