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參數(shù)資料
| 型號： | 935167440557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, SOT-318-1, QFP-80 |
| 文件頁數(shù)： | 24/112頁 |
| 文件大小： | 707K |
| 代理商： | 935167440557 |
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1996 Jun 27
19
Philips Semiconductors
Product specication
8-bit microcontroller with on-chip CAN
P8xCE598
Fig.9 Functional diagram of Pulse Width Modulated outputs.
handbook, full pagewidth
MGA154
I
N
T
E
R
N
A
L
B
U
S
fclk
PWMP
PWM1
PRESCALER
8-BIT COUNTER
1/2
PWM0
8-BIT COMPARATOR
OUTPUT
BUFFER
PWM1
OUTPUT
BUFFER
PWM0
10 ANALOG-TO-DIGITAL CONVERTER (ADC)
The analog input circuitry consists of an 8-input analog
multiplexer and an ADC with 10-bit resolution. The analog
reference voltage and analog power supplies are
connected via separate input pins. The conversion takes
50 machine cycles i.e. 37.5
s at 16 MHz oscillator
frequency. The input voltage swing is from 0 V to AVDD.
The ADC is controlled using the ADCON control register.
Register bits ADCON.0 to ADCON.2 select the input
channels of the analog multiplexer (see Fig.10).
The completion of the 10-bit analog-to-digital conversion is
flagged by ADCI in the ADCON register and the result is
stored in the SFR ADCH (upper 8-bits) and the 2 lower bits
(ADC.1 and ADC.0) in register ADCON.
An analog-to-digital conversion in progress is unaffected
by an external or software ADC start. The result of a
completed conversion remains unchanged provided
ADCI = HIGH. While ADCI or ADCS are HIGH, a new ADC
START will be blocked and consequently lost. An
analog-to-digital conversion already in progress is aborted
when the Idle or Power-down mode is entered.
The result of a completed conversion (ADCI = HIGH)
remains unaffected during the Idle mode.
The LOW-to-HIGH transition of STADC is recognized at
the end of a machine cycle and the conversion
commences at the beginning of the next cycle. When a
conversion is initiated by software, the conversion starts at
the beginning of the machine cycle following the
instruction that sets ADCS.
The next two machine cycles are used to initiate the
converter. At the end of this first cycle, the ADCS status
flag is set to HIGH while the conversion is in progress.
Sampling of the analog input commences at the end of the
second cycle.
During the next eight machine cycles, the voltage at the
previously selected pin of Port 5 is sampled and this input
voltage should be stable in order to obtain a useful sample.
In any case, the input voltage slew rate must be less than
10 V/ms (5 V conversion range) in order to prevent an
undefined result. The conversion takes four machine
cycles per bit.
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