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| 型號(hào)： | 935167440557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, SOT-318-1, QFP-80 |
| 文件頁(yè)數(shù)： | 37/112頁(yè) |
| 文件大小： | 707K |
| 代理商： | 935167440557 |
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1996 Jun 27
30
Philips Semiconductors
Product specication
8-bit microcontroller with on-chip CAN
P8xCE598
Table 29 Hardware blocks of the CAN-controller (see Fig.14)
NAME
BLOCK
DESCRIPTION
Interface Management Logic
IML
Interprets commands from the CPU, allocates the message buffers
(TBF, RBF0 and RBF1) and provides interrupts and status information to the
microcontroller.
Transmit Buffer
TBF
10 bytes memory into which the CPU writes messages which are to be
transmitted over the CAN network.
Receive Buffers (0 and 1)
RBF0
RBF0 and RBF1 are each 10 bytes memories which are alternatively used to
store messages received from the CAN network.
The CPU can process one message while another is being received.
RBF1
Bit Stream Processor
BSP
Is a sequencer, controlling the data stream between the Transmit Buffer,
Receive Buffers (parallel data) and the CAN-bus (serial data).
Bit Timing Logic
BTL
Synchronizes the CAN-controller to the bitstream on the CAN-bus.
Transceiver Control Logic
TCL
Controls the output driver.
Error Management Logic
EML
Performs the error connement according to the CAN-protocol.
Fig.14 Block diagram of the P8xCE598 on-chip CAN-controller.
handbook, full pagewidth
MGA159
INTERFACE
MANAGEMENT
LOGIC
TRANSCEIVER
LOGIC
TRANSMIT
BUFFER
BIT TIMING
LOGIC
2
ON - CHIP
CAN
CONTROLLER
RECEIVE
BUFFER 0
RECEIVE
BUFFER 1
BIT STREAM
PROCESSOR
ERROR
MANAGEMENT
LOGIC
address
data
CRX0
and
CRX1
CTX0
and
CTX1
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