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參數(shù)資料
| 型號： | 935167440557 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, OTPROM, 16 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 14 X 20 MM, 2.70 MM HEIGHT, PLASTIC, SOT-318-1, QFP-80 |
| 文件頁數(shù)： | 52/112頁 |
| 文件大?。?/td> | 707K |
| 代理商： | 935167440557 |
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1996 Jun 27
44
Philips Semiconductors
Product specication
8-bit microcontroller with on-chip CAN
P8xCE598
13.5.10 BUS TIMING REGISTER 1(BTR1)
The contents of Bus Timing Register 1 defines the length
of the bit period, the location of the sample point and the
number of samples to be taken at each sample point.
This register can be accessed (read/write) if the Reset
Request bit is set HIGH (present).For further information
on bus timing, see Sections 13.5.9 and 13.5.18.
Table 47 Bus Timing Register 1 (address 7)
Table 48 Description of the BTR1 bits
76543210
SAM
TSEG2.2
TSEG2.1
TSEG2.0
TSEG1.3
TSEG1.2
TSEG1.1
TSEG1.0
BIT
SYMBOL
FUNCTION
7
SAM
Sampling. If the bit SAM is:
HIGH (3 samples), then three samples are taken. This is recommended for
slow/medium speed buses (SAE class A and B) where ltering of spikes on the
bus-line is benecial (see Section 13.5.19.6).
LOW (1 sample), the bus is sampled once.
This is recommended for high speed buses (SAE class C).
6
TSEG2.2
Time Segment 1 (TSEG1) and Time Segment 2 (TSEG2).
TSEG1 determines the number of clock cycles per bit period and the location of the
sample point:
TSEG2 determines the number of clock cycles per bit period and the location of the
sample point:
5
TSEG2.1
4
TSEG2.0
3
TSEG1.3
2
TSEG1.2
1
TSEG1.1
0
TSEG1.0
t
TSEG1
t
SCL 8TSEG1.3
4TSEG1.2
2TSEG1.1
TSEG1.0
1
+++
+
()
=
t
TSEG2
t
SCL 4 TSEG2.2
2TSEG2.1
TSEG2.0
1
++
+
()
=
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