
2000
Mar
15
6
Philips
Semiconductors
Preliminar
y
specication
P
AL/NTSC/SECAM
video
decoder
with
adaptiv
e
P
AL/NTSC
comb
lter
,VBI-data
slicer
and
high
perf
or
mance
scaler
SAA7114H
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6
BLOCK
DIA
GRAM
u
llpagewidth
MHB528
FIR-PREFILTER
PRESCALER
AND
SCALER BCS
GENERAL PURPOSE
VBI-DATA SLICER
VIDEO/TEXT
ARBITER
TEXT
FIFO
VIDEO
FIFO
PROGRAMMING
REGISTER
ARRAY
A/B
REGISTER
MUX
EVENT CONTROLLER
IMAGE
PORT
PIN
MAPPING
X PORT I/O FORMATTING
EXPANSION PORT PIN MAPPING
I/O CONTROL
I2C-BUS
REAL-TIME OUTPUT
LLC
13
AI2D
LINE
FIFO
BUFFER
VERTICAL
SCALING
HORIZONTAL
FINE
(PHASE)
SCALING
32
to
8(16)
MUX
47
ITRI
21
AGND
19
AI1D
22
AOUT
10
AI24
12
AI23
14
AI22
16
AI21
18
AI12
20
AI11
6
XTALO
7
XTALI
4
XTOUT
27
CE
30
28
97
TCK
98
TMS
99
TDI
3
VDD(XTAL)
8
VSS(XTAL)
5
VDDD(ICO1)
to
VDDD(ICO6)
33, 43,
58, 68,
83, 93
VDDD(EP1)
to
VDDD(EP4)
1, 25,
51, 75
VDDA0
to
VDDA2
23, 17,
11
VSSD(ICO1)
to
VSSD(ICO3)
38, 63,
88
VSSD(EP1)
to
VSSD(EP4)
26, 50,
76, 100
VSSA0
to
VSSA2
24,
15, 9
AMXCLK
41
TDO
2
AMCLK
37
ALRCLK
40
ASCLK
39
LLC2
29
RTCO
36
RTS0
34
RTS1
35
XCLK
94
XDQ
95
81, 82,
84 to 87
89, 90
XRH
92
XRV
91
XRDY
96
SDA
32
SCL
31
TEST5
79
TEST4
78
TEST3
77
TEST2
74
TEST1
73
TEST0
44
64 to 67,
69 to 72
XTRI
80
chrominance of 16-bit input
BOUNDARY
SCAN
TEST
CLOCK GENERATION
AND
POWER-ON CONTROL
ANALOG
DUAL
ADC
DIGITAL
DECODER
WITH
ADAPTIVE
COMB
FILTER
AUDIO
CLOCK
GENERATION
42
ITRDY
45
ICLK
49
IGP1
48
IGP0
52
IGPV
53
IGPH
46
IDQ
54 to 57,
59 to 62
IPD[7:0]
HPD[7:0]
XPD[7:0]
RES
SAA7114H
TRST
(1)
Fig.1 Block diagram.
(1) The pins RTCO and ALRCLK are used for configuration of the I2C-bus interface
and the definition of the crystal oscillator frequency at RESET (pin strapping).