參數(shù)資料
型號(hào)： 935262451518
廠商： NXP SEMICONDUCTORS
元件分類： 顏色信號(hào)轉(zhuǎn)換
英文描述： COLOR SIGNAL DECODER, PQFP100
封裝： 14 X 14 X 1.40 MM, PLASTIC, SOT-407, LQFP-100
文件頁數(shù)： 4/144頁
文件大小： 592K
代理商： 935262451518
2000 Mar 15
101
Philips Semiconductors
Preliminary specication
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb lter, VBI-data slicer and high performance scaler
SAA7114H
15.2.20 SUBADDRESS 13H
Table 57 RT/X-port output control; 13H[7:0]
BIT
DESCRIPTION
SYMBOL
VALUE
FUNCTION
D7
RTCO output enable
RTCE
0
3-state
1
enabled
D6
X-port XRH output
selection
XRHS
0
HREF (see Fig.23)
1
HS:
programmable width in LLC8 steps via HSB[7:0]06H[7:0]
and HSS[7:0]07H[7:0]
fine position adjustment in LLC2 steps via
HDEL[1:0]11H[5:4] (see Fig.23)
D[5:4] X-port XRV output
selection
XRVS[1:0]
00
V123 (see Figs 21 and 22)
01
ITU 656 related eld ID (see Figs 21 and 22)
10
inverted V123
11
inverted ITU 656 related eld ID
D3
horizontal lock indicator
selection
HLSEL
0
copy of inverted HLCK status bit (default)
1
fast horizontal lock indicator (for special applications only)
D[2:0] XPD7 to XPD0 (port
output format selection);
see Section 9.4
OFTS[2:0]
000
ITU 656
001
ITU 656 like format with modied eld blanking according to
VGATE position (programmable via VSTA8 to VSTA0,
VSTO8 to VSTO0 and VGPS, subaddresses 15H,
16H and 17H)
010
YUV 4:2:2 8-bit format (no SAV/EAV codes inserted)
011
reserved
100
multiplexed AD2/AD1 bypass (bits 8 to 1) dependent on
mode settings; if both ADCs are selected AD2 is output at
CREF = 1 and AD1 is output at CREF = 0
101
multiplexed AD2/AD1 bypass (bits 7 to 0) dependent on
mode settings; if both ADCs are selected AD2 is output at
CREF = 1 and AD1 is output at CREF = 0
110
reserved
111
multiplexed ADC MSB/LSB bypass dependent on mode
settings; only one ADC should be selected at a time;
ADx8 to ADx1 are outputs at CREF = 1 and ADx7 to ADx0
are outputs at CREF = 0
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