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| 型號(hào)： | 935262451518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類(lèi)： | 顏色信號(hào)轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP100 |
| 封裝： | 14 X 14 X 1.40 MM, PLASTIC, SOT-407, LQFP-100 |
| 文件頁(yè)數(shù)： | 22/144頁(yè) |
| 文件大?。?/td> | 592K |
| 代理商： | 935262451518 |
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2000 Mar 15
118
Philips Semiconductors
Preliminary specication
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb lter, VBI-data slicer and high performance scaler
SAA7114H
15.5.6
SUBADDRESSES 91H TO 93H
Table 99 X-port formats and conguration; register set A (91H[2:0]) and B (C1H[2:0])
Notes
1. X = don’t care.
2. FSC2 and FSC1 only to be used, if X-port input source don’t provide chroma information for every input line. X-port
input stream must contain dummy chroma bytes.
Table 100 X-port formats and conguration; register set A (91H[7:3]) and B (C1H[7:3])
X = don’t care.
SCALER INPUT FORMAT AND CONFIGURATION FORMAT
CONTROL
CONTROL BITS D2 TO D0(1)
FSC2(2)
FSC1(2)
FSC0
Input is YUV 4 : 2 : 2 like sampling scheme
X
0
Input is YUV 4 : 1 : 1 like sampling scheme
X
1
Chroma is provided every line, default
00
X
Chroma is provided every 2nd line
0
1
X
Chroma is provided every 3rd line
1
0
X
Chroma is provided every 4th line
1
X
SCALER INPUT FORMAT AND CONFIGURATION SOURCE
SELECTION
CONTROL BITS D7 TO D3
CONLV
HLDFV
SCSRC1 SCSRC0
SCRQE
Only if XRQT[83H[2]] = 1: scaler input source reacts on
SAA7114H request
XXXX
0
Scaler input source is a continuous data stream, which cannot
be interrupted (must be logic 1, if SAA7114H decoder part is
source of scaler or XRQT[83H[2]] = 0)
XXXX
1
Scaler input source is data from decoder, data type is
provided according to Table 14
XX
0
X
Scaler input source is YUV data from X-port
X
0
1
X
Scaler input source is raw digital CVBS from selected analog
channel, for backward compatibility only, further use is not
recommended
XX
1
0
X
Scaler input source is raw digital CVBS (or 16-bit Y + UV, if no
16-bit output are active) from X-port
XX
1
X
SAV/EAV code bits D6 and D5 (F and V) may change
between SAV and EAV
X
0
XXX
SAV/EAV code bits D6 and D5 (F and V) are synchronized to
scalers output line start
X
1
XXX
SAV/EAV code bit D5 (V) and V-gate on pin IGPV as
generated by the internal processing, see Fig.36
0
XXXX
SAV/EAV code bit D5 (V) and V-gate are inverted
1
XXXX
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