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參數(shù)資料
| 型號(hào)： | 935262451518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號(hào)轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP100 |
| 封裝： | 14 X 14 X 1.40 MM, PLASTIC, SOT-407, LQFP-100 |
| 文件頁(yè)數(shù)： | 77/144頁(yè) |
| 文件大?。?/td> | 592K |
| 代理商： | 935262451518 |
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2000 Mar 15
38
Philips Semiconductors
Preliminary specication
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb lter, VBI-data slicer and high performance scaler
SAA7114H
Raw VBI-data will be handled as specific input format and
need an own programming page (= own task).
In VBI pass through operation the processing of prescaler
and vertical scaling has to be set to no-processing, but the
horizontal fine scaling VPD can be activated. Upscaling
(oversampling, zooming), free of frequency folding, up to
factor 3.5 can be achieved, as required by some software
data slicing algorithms.
These raw samples are transported through the image
port as valid data and can be output as Y only format.
The lines are framed by SAV and EAV codes.
8.3.1
ACQUISITION CONTROL AND TASK HANDLING
(SUBADDRESSES 80H, 90H, 94H TO 9FH AND
C4H TO CFH)
The acquisition control receives horizontal and vertical
synchronization signals from the decoder section or from
the X-port. The acquisition window is generated via pixel
and line counters at the appropriate places in the data
path. From X-port only qualified pixels and lines
(= lines with qualified pixel) are counted.
The acquisition window parameters are:
Signal source selection regarding input video stream
and formats from the decoder, or from X-port
(programming bits SCSRC[1:0]91H[5:4] and
FSC[2:0]91H[2:0])
Remark: The input of raw VBI-data from internal
decoder should be controlled via the decoder output
formatter and the LCR registers (see Section 8.2
“Decoder output formatter”)
Vertical offset defined in lines of the video source,
parameter YO[11:0]99H[3:0]98H[7:0]
Vertical length defined in lines of the video source,
parameter YS[11:0]9BH[11:8]9AH[7:0]
Vertical length defined in number of target lines, as
result of vertical scaling, parameter
YD[11:0]9FH[11:8]9EH[7:0]
Horizontal offset defined in number of pixels of the video
source, parameter XO[11:0]95H[3:0]94H[7:0]
Horizontal length defined in number of pixels of the
video source, parameter XS[11:0]97H[3:0]96H[7:0]
Horizontal destination size, defined in target pixels after
fine scaling, parameter XD[11:0]9DH[3:0]9CH[7:0].
The source start offset (XO11 to XO0, YO11 to YO0)
opens the acquisition window, and the target size
(XD11 to XD0, YD11 to YD0) closes the window, but the
window is cut vertically, if there are less output lines than
expected. The trigger events for the pixel and line counts
are the horizontal and vertical reference edges as defined
in subaddress 92H.
The task handling is controlled by subaddress 90H (see
Section 8.3.1.2).
8.3.1.1
Input eld processing
The trigger event for the field sequence detection from
external signals (X-port) are defined in subaddress 92H.
From the X-port the state of the scalers H-reference signal
at the time of the V-reference edge is taken as field
sequence identifier FID. For example, if the falling edge of
the XRV input signal is the reference and the state of XRH
input is logic 0 at that time, the detected field ID is logic 0.
The bits XFDV[92H[7]] and XFDH[92H[6]] are defining the
detection event and state of the flag from the X-port.
For the default setting of XFDV and XFDH at ‘00’ the state
of the H-input at the falling edge of the V-input is taken.
The scaler directly gets a corresponding field ID
information from the SAA7114H decoder path.
The FID flag is used to determine, whether the first or
second field of a frame is going to be processed within the
scaler and it is used as trigger condition for the task
handling (see bits STRC[1:0]90H[1:0]).
According to ITU 656, FID at logic 0 means first field of a
frame. To ease the application, the polarities of the
detection results on the X-port signals and the internal
decoder ID can be changed via XFDH.
As the V-sync from the decoder path has a half line timing
(due to the interlaced video signal), but the scaler
processing only knows about full lines, during 1st fields
from the decoder the line count of the scaler possibly shifts
by one line, compared to the 2nd field. This can be
compensated by switching the V-trigger event, as defined
by XDV0, to the opposite V-sync edge or by using the
vertical scalers phase offsets. The vertical timing of the
decoder can be seen in Figs 21 and 22.
As the H and V reference events inside the ITU 656 data
stream (from X-port) and the real-time reference signals
from the decoder path are processed differently, the
trigger events for the input acquisition also have to be
programmed differently.
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