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參數(shù)資料
| 型號： | 935262451518 |
| 廠商： | NXP SEMICONDUCTORS |
| 元件分類： | 顏色信號轉(zhuǎn)換 |
| 英文描述： | COLOR SIGNAL DECODER, PQFP100 |
| 封裝： | 14 X 14 X 1.40 MM, PLASTIC, SOT-407, LQFP-100 |
| 文件頁數(shù)： | 95/144頁 |
| 文件大?。?/td> | 592K |
| 代理商： | 935262451518 |
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2000 Mar 15
54
Philips Semiconductors
Preliminary specication
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb lter, VBI-data slicer and high performance scaler
SAA7114H
Table 17 Limiting range on I-port
LIMIT STEP
ILLV[85H[5]]
VALID RANGE
SUPPRESSED CODES (HEXADECIMAL VALUE)
DECIMAL VALUE
HEXADECIMAL VALUE
LOWER RANGE
UPPER RANGE
0
1 to 254
01 to FE
00
FF
1
8 to 247
08 to F7
00 to 07
F8 to FF
8.5.2
VIDEO FIFO (SUBADDRESS 86H)
The video FIFO at the scaler output contains 32 Dwords.
That corresponds to 64 pixels in 16-bit YUV 4:2:2
format. But as the entire scaler can act as pipeline buffer,
the actually available buffer capacity for the image port is
much higher, and can exceed beyond a video line.
The image port, and the video FIFO, can operate with the
video source clock (synchronous mode) or with externally
provided clock (asynchronous, and burst mode), as
appropriate for the VGA controller or attached frame
buffer.
The video FIFO provides 4 internal flags, reporting to
which extent the FIFO is actually filled. These are:
The FIFO Almost Empty (FAE) flag
The FIFO Combined Flag (FCF) or FIFO filled, which is
set at almost full level and reset, with hysteresis, only
after the level crosses below the almost empty mark
The FIFO Almost Full (FAF) flag
The FIFO Overflow (FOVL) flag.
The trigger levels for FAE and FAF are programmable by
FFL[1:0]86H[3:2] (16, 24, 28, full) and FEL[1:0]86H[1:0]
(16, 8, 4, empty).
The state of this flag can be seen on the
pins IGP0 or IGP1. The pin mapping is defined by
subaddresses 84H and 85H (see Section 9.5).
8.5.3
TEXT FIFO
In the text FIFO the data of the terminal VBI-data slicer are
collected before the transmission over the I-port is
requested (normally before the video window starts). It is
partitioned into two FIFO sections. A complete line is filled
into the FIFO, before a data transfer is requested. So
normally, one line text data is ready for transfer, while the
next text line is collected. So sliced text data are delivered
as a block of qualified data, without any qualification gaps
in the byte stream of the I-port.
The decoded VBI-data is collected in the dedicated
VBI-data FIFO. After capture of a line is completed, the
FIFO can be streamed through the image port, preceded
by a header, telling line number and standard.
The VBI-data period can be signalled via the sliced data
flag on pin IGP0 or IGP1. The decoded VBI-data is lead by
the ITU ancillary data header (DID[5:0]5DH[5:0] at value
<3EH) or by SAV/EAV codes selectable by DID[5:0] at
value 3EH or 3FH. IGP0 or IGP1 is set, if the first byte of
the ANC header is valid on the I-port bus. It is reset, if an
SAV occurs. So it may frame multiple lines of text data
output, in case video processing starts with a distance of
several video lines to the region of text data. Valid sliced
data from the text FIFO are available on the I-port as long
as the IGP0 or IGP1 flag is set and the data qualifier is
active on pin IDQ.
The decoded VBI-data are presented in two different data
formats, controlled by bit RECODE.
RECODE = 1: values 00H and FFH will be recoded to
even parity values 03H and FCH
RECODE = 0: values 00H and FFH may occur in the
data stream as detected.
8.5.4
VIDEO AND TEXT ARBITRATION (SUBADDRESS 86H)
Sliced text data and scaled video data are transferred over
the same bus, the I-port. The mixed transfer is controlled
by an arbitration circuitry. If the video data are transferred
without any interrupt and the video FIFO does not need to
buffer any output pixel, the text data are inserted after an
end of a scaled video line, normally during the blanking
interval of the video.
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