
2000 Mar 15
127
Philips Semiconductors
Preliminary specication
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb lter, VBI-data slicer and high performance scaler
SAA7114H
Table 126 Vertical luminance phase offset ‘00’; register set A (BCH[7:0]) and B (ECH[7:0])
16 PROGRAMMING START SET-UP
16.1
Decoder part
The given values force the following behaviour of the SAA7114H decoder part:
The analog input AI11 expects an NTSC M, PAL BDGHI or SECAM signal in CVBS format; analog anti-alias filter and
AGC active
Automatic field detection enabled
Standard ITU 656 output format enabled on expansion (X) port
Contrast, brightness and saturation control in accordance with ITU standards
Adaptive comb filter for luminance and chrominance activated
Pins LLC, LLC2, XTOUT, RTS0, RTS1 and RTCO are set to 3-state.
Table 127 Decoder part start set-up values for the three main standards
VERTICAL LUMINANCE PHASE
OFFSET
CONTROL BITS D7 TO D0
YPY07
YPY06
YPY05
YPY04
YPY03
YPY02
YPY01
YPY00
Offset = 0
0
000000
Offset = 32
32 = 1 line
0
100000
Offset = 255
32 lines
1
111111
SUB
ADDRESS
(HEX)
REGISTER
FUNCTION
BIT NAME(1)
VALUES (HEX)
NTSC M PAL BDGHI
SECAM
00
chip version
ID07 to ID04
read only
01
horizontal increment
delay
X, X, X, X, IDEL3 to IDEL0
08
02
analog input control 1
FUSE1 and FUSE0, GUDL1 to GUDL0,
MODE3 to MODE0
C0
03
analog input control 2
X, HLNRS, VBSL, WPOFF, HOLDG,
GAFIX, GAI28 and GAI18
10
04
analog input control 3
GAI17 to GAI10
90
05
analog input control 4
GAI27 to GAI20
90
06
horizontal sync start
HSB7 to HSB0
EB
07
horizontal sync stop
HSS7 to HSS0
E0
08
sync control
AUFD, FSEL, FOET, HTC1, HTC0,
HPLL, VNOI1 and VNOI0
98
09
luminance control
BYPS, YCOMB, LDEL, LUBW,
LUFI3 to LUFI0
40
1B
0A
luminance brightness
control
DBRI7 to DBRI0
80
0B
luminance contrast
control
DCON7 to DCON0
44
0C
chrominance saturation
control
DSAT7 to DSAT0
40