參數(shù)資料
型號: 935262451518
廠商: NXP SEMICONDUCTORS
元件分類: 顏色信號轉(zhuǎn)換
英文描述: COLOR SIGNAL DECODER, PQFP100
封裝: 14 X 14 X 1.40 MM, PLASTIC, SOT-407, LQFP-100
文件頁數(shù): 3/144頁
文件大?。?/td> 592K
代理商: 935262451518
2000 Mar 15
100
Philips Semiconductors
Preliminary specication
PAL/NTSC/SECAM video decoder with adaptive PAL/NTSC
comb lter, VBI-data slicer and high performance scaler
SAA7114H
Table 56 RT signal control: RTS1 output; 12H[7:4]
The polarity of any signal on RTS1 can be inverted via RTP1[11H[6]].
Note
1. Function of HL is selectable via HLSEL[13H[3]]:
a) HLSEL = 0: HL is standard horizontal lock indicator.
b) HLSEL = 1: HL is fast horizontal lock indicator (use is not recommended for sources with unstable timebase e.g.
VCRs).
RTS1 OUTPUT
RTSE13 RTSE12 RTSE11 RTSE10
3-state
0000
Constant LOW
0
1
CREF (13.5 MHz toggling pulse; see Fig.23)
0
1
0
CREF2 (6.75 MHz toggling pulse; see Fig.23)
0
1
HL; horizontal lock indicator (note 1):
0
1
0
HL = 0: unlocked
HL = 1: locked
VL; vertical and horizontal lock:
0
1
0
1
VL = 0: unlocked
VL = 1: locked
DL, vertical and horizontal lock and colour detected:
0
1
0
DL = 0: unlocked
DL = 1: locked
Reserved
0
1
HREF, horizontal reference signal; indicates 720 pixels valid data on the
expansion port. The positive slope marks the beginning of a new active
line. HREF is also generated during the vertical blanking interval
(see Fig.23).
1000
HS:
1001
programmable width in LLC8 steps via HSB[7:0]06H[7:0] and
HSS[7:0]07H[7:0]
fine position adjustment in LLC2 steps via HDEL[1:0]11H[5:4]
(see Fig.23)
HQ; HREF gated with VGATE
1
0
1
0
Reserved
1
0
1
V123; vertical sync (see vertical timing diagrams Figs 21 and 22)
1
0
VGATE; programmable via VSTA[8:0]17H[0]15H[7:0],
VSTO[8:0]17H[1]16H[7:0] and VGPS[17H[2]]
1101
LSBs of the 9-bit ADC’s
1
0
FID; position programmable via STA[8:0]17H[0]15H[7:0]; see vertical timing
diagrams Figs 21 and 22
1111
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