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參數(shù)資料
| 型號： | 9880 |
| 廠商： | Intel Corp. |
| 英文描述： | Advanced 10/100 Repeater with Intergrated Management |
| 中文描述： | 高級10/100中繼器與綜合管理 |
| 文件頁數(shù)： | 114/118頁 |
| 文件大?。?/td> | 1648K |
| 代理商： | 9880 |
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LXT9860/9880
—
Advanced 10/100 Repeater with Integrated Management
114
Datasheet
Document #: 248987
Revision#: 003
Rev Date: 08/07/01
Table 86. Interrupt Status Register Bit Definitions
Bit
Name
Type
1, 2
Description
Default
31:6
Reserved
R/W
Reserved
0
5
JABINT
R/W
Jabber Interrupt
A
‘
1
’
indicates that a port is in jabber state.
During 100 Mbps operation, jabber occurs when any receiver
remains active for more than 57,500 bit times. The LXT98x0
exits this state when all receivers return to the idle condition.
During 10 Mbps operation, jabber occurs when any port remains
actively transmitting for longer than 40,000 to 75,000 bit times.
The LXT98x0 asserts a minimum-IFG idle period when a port is
jabbering.
0
4
ISOLINT
R/W
Isolate Interrupt
A
‘
1
’
indicates that a port has been isolated (100 Mbps only).
The LXT98x0 isolates any port transmitting more than two
successive false carrier events. A false carrier event is defined
as a packet not starting with a /J/K symbol pair.
0
3
PARTINT
R/W
Partition Interrupt
A
‘
1
’
indicates a port has been partitioned.
In 100 Mbps operation, the LXT98x0 partitions any port
participating in excess of 60 consecutive collisions.
In 10 Mbps operation, the LXT98x0 partitions any port
participating in excess of 31 consecutive collisions.
Once partitioned, the LXT98x0 continues monitoring and
transmitting to the port, but does not repeat data received from
the port until it properly un-partitions.
0
2
FCCINT
R/W
False Carrier Count Interrupt
A
‘
1
’
indicates a port has received too many false carrier events.
0
1
SACHNGINT
R/W
Source Address Change Interrupt
A
‘
1
’
indicates that a port address changed from that stored in
the last Source Address register.
0
0
SPDCHNGINT
R/W
Speed Change Interrupt
A
‘
1
’
indicates a port speed change was detected.
0
1. R = Read only; W = Write only, R/W = Read/Write., LH = Latch High, LL = Latch Low, SC = Self Clearing
2. If Register Clear bit is set to
‘
1
’
, then clearing of the associated bit is done by writing
‘
1
’
to it, otherwise this
register self clears upon read. Register Clear (Bit 11) is set through the Repeater Configuration Register.
(Refer to
Table 75 on page 109
.)
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