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參數(shù)資料
| 型號(hào)： | 9880 |
| 廠商： | Intel Corp. |
| 英文描述： | Advanced 10/100 Repeater with Intergrated Management |
| 中文描述： | 高級(jí)10/100中繼器與綜合管理 |
| 文件頁數(shù)： | 30/118頁 |
| 文件大小： | 1648K |
| 代理商： | 9880 |
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LXT9860/9880
—
Advanced 10/100 Repeater with Integrated Management
30
Datasheet
Document #: 248987
Revision#: 003
Rev Date: 08/07/01
Table 11. Miscellaneous Signal Descriptions
Pin
Symbol
Type
1, 2
Description
53
RESET
I
Schmitt
Reset.
This active Low input causes internal circuits, state
machines and counters to reset (address tracking registers do not
reset). On power-up, devices should not be brought out of reset
until the power supply stabilizes to 3.3V. When there are multiple
devices, it is recommended all be supplied by a common reset
driven by an
‘
LS14 or similar device.
54
CLK25
I
Schmitt
25 MHz system clock.
Refer to
Table 29 on page 75
for clock
requirements.
72
73
CHIPID0
CHIPID1
I
PD
Chip ID.
These pins assign unique Chip IDs to as many as four
devices on a single board. One device on each board must be
assigned ChipID = 00. See
“
Serial Management I/F
”
on page 52
.
33
CONFIG(0) /
CFG_DT
I
PD
Configuration Register Input 0.
The CONFIG[1:0] inputs allow
the user to store system-specific information (board type, plug-in
cards, status, etc.) in the Serial Configuration Register (hex
address AC). This register may be read remotely through the
Serial Management Interface (SMI).
Configuration Bus Data.
Used in conjunction with CFG_CLK
and CFG_LD, these pins provide an expansion capability for the
functionality of CONFIG[1:0]. Using an external Parallel-to-Serial
device, up to 8 Configuration inputs can be brought to the SMI for
user access.
The Configuration Mode Select bit (Bit 14) in the Repeater
Configuration Register is used to choose between CONFIG[1:0]
and CFG bus modes. (See
Table 75 on page 109
.)
25
CONFIG(1) /
CFG_LD
I/O
PD
Configuration Register Input 1.
The CONFIG[1:0] inputs allow
the user to store system-specific information (board type, plug-in
cards, status, etc.) in the Repeater Serial Configuration register.
This register may be read remotely through the Serial
Management Interface (SMI).
Configuration Bus Load
(active Low)
.
Used in conjunction with
CFG_CLK and CFG_DT, this active Low pin provides an
expansion capability for the functionality of CONFIG[1:0]. Using
an external Parallel-to-Serial device, up to 8 Config. inputs can be
brought to the SMI for user access.
The Configuration Mode Select bit (Bit 14) in the Repeater
Configuration Register is used to choose between CONFIG[1:0]
and CFG bus modes. See
Table 75 on page 109
.)
1. I = Input, O = Output, I/O = Input/Output, D = Digital, A = Analog, AI = Analog Input,
A I/O = Analog Input/Output, OD = Open Drain, OS = Open Source, PD = Pull Down, PU = Pull Up.
NC = No Clamp. Pad does not clamp input in the absence of power.
2. Pins are 5V tolerant, unless indicated.
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