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| 型號(hào)： | 9880 |
| 廠商： | Intel Corp. |
| 英文描述： | Advanced 10/100 Repeater with Intergrated Management |
| 中文描述： | 高級(jí)10/100中繼器與綜合管理 |
| 文件頁(yè)數(shù)： | 31/118頁(yè) |
| 文件大小： | 1648K |
| 代理商： | 9880 |
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Advanced 10/100 Repeater with Integrated Management
—
LXT9860/9880
Datasheet
Document #: 248987
Revision#: 003
Rev Date: 08/07/01
31
3.0
Functional Description
3.1
Introduction
As a fully integrated IEEE 802.3 compliant repeater capable of 10 Mbps and 100 Mbps operation,
the LXT98x0 is a versatile device allowing great flexibility in Ethernet design solutions.
Figure 3
shows a typical application. Refer to
“
Application Information
”
on page 61
for specific circuit
implementations.
This multi-port repeater provides six (LXT9860) or eight (LXT9880) 10BASE-T/100BASE-TX
ports. In addition, each device also provides two Media Independent Interface (MII) expansion
ports that may be connected to 10/100 MACs.
The LXT98x0 provides two repeater state machines and two Inter-Repeater Backplanes (IRB) on a
single chip
—
one for 10 Mbps and one for 100 Mbps operation. The 100 Mbps repeater meets IEEE
802.3 Class II requirements. Each port
’
s operating speed may be selected independently. The auto-
negotiation capability of the LXT98x0 allows it to communicate with connected nodes and
configure itself accordingly.
The LXT98x0 supports RMON by providing on-chip counters and hardware assistance for a fully
managed environment. The segmented backplane simplifies dual-speed operation, and allows
multiple devices to be stacked and function as one logical Class II repeater. Up to 240 ports (192
TP ports and 48 MII ports) can be supported in a single stack.
82
CFG_CLK/
LEDCLK
O
Configuration Bus Clock.
Refer to CFG_DT and CFG_LD pin
description. CFG_CLK pulses whenever a read of the Serial
Configuration Register occurs. Refer to
“
Serial Configuration
Interface
”
on page 60
.
LED Clock
. Serial data stream clock for external Serial-to-
Parallel LED drivers. Refer to
Table 8
for details.
182
IRQ
O
OD
Interrupt request.
Active Low interrupt. Refer to register section
for criteria and clearing options.
Requires an external pull-up resistor.
51,
52,
66,178
NC
-
No Connects.
Leave these pins unconnected.
Table 11. Miscellaneous Signal Descriptions (Continued)
Pin
Symbol
Type
1, 2
Description
1. I = Input, O = Output, I/O = Input/Output, D = Digital, A = Analog, AI = Analog Input,
A I/O = Analog Input/Output, OD = Open Drain, OS = Open Source, PD = Pull Down, PU = Pull Up.
NC = No Clamp. Pad does not clamp input in the absence of power.
2. Pins are 5V tolerant, unless indicated.
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