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參數(shù)資料
| 型號(hào)： | 9880 |
| 廠商： | Intel Corp. |
| 英文描述： | Advanced 10/100 Repeater with Intergrated Management |
| 中文描述： | 高級(jí)10/100中繼器與綜合管理 |
| 文件頁(yè)數(shù)： | 34/118頁(yè) |
| 文件大?。?/td> | 1648K |
| 代理商： | 9880 |
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LXT9860/9880
—
Advanced 10/100 Repeater with Integrated Management
34
Datasheet
Document #: 248987
Revision#: 003
Rev Date: 08/07/01
When used in 100BASE-TX applications, the LXT98x0 sends and receives a continuous,
scrambled 125Mbaud MLT-3 waveform on this interface. In the absence of data, IDLE symbols are
sent and received in order to maintain the link.
When used in 10BASE-T applications, the LXT98x0 sends and receives a non-continuous, 10
Mbaud Manchester-encoded waveform. To maintain link during idle periods, the LXT98x0 sends
link pulses every 16 ms, and expects to receive them every 10 to 20ms. Each 10BASE-T port
automatically detects and sends link pulses, and disables its transmitter if link pulses are not
detected. Each receiver can also be configured to ignore link pulses, and leave its transmitter
enabled all the time (link pulse transmission cannot be disabled). Each 10BASE-T port can detect
and automatically correct for polarity reversal on the TPIP/N inputs. The 10BASE-T interface
provides integrated filters using Intel
’
s patented filter technology. These filters facilitate low-cost
stack designs to meet EMI requirements.
3.3.2
Media Independent Interface
The LXT98x0 has two identical MII interfaces. The MII has been designed to allow expansion to a
Media Access Controller (MAC) as shown in
Figure 4
. This interface is not MDIO/MDC capable.
Management is provided via a serial controller interface. These MII ports can be set via hardware
tie ups/downs to be either 10 Mbps or 100 Mbps100 Mbps. The statistics kept for these ports are
the same as for the other 10/100 ports, except Isolation, Partition, and Symbol Error. These ports
are not the full MII drive strength and are intended only for point-to-point links. Serial terminations
are recommended.
3.3.3
Serial Management Interface
The Serial Management Interface (SMI) provides system access to the status, control and statistic
gathering abilities of the LXT98x0. This interface allows multiple devices to be managed from a
common line, and uses the minimum number of signals (2) for ease of stack design.
The interface itself consists of two digital NRZ signals
—
clock and data. Refer to
Table 7 on
page 26
for SMI pin assignments and signal descriptions. Data is framed into HDLC-like packets,
with a start/stop flag, header and CRC field for error checking. Zero-bit insertion/removal is used.
The interface can operate at any speed from 0 to 2 MHz. (
“
0 MHz
”
means the clock need not be
continuous. It can be started, stopped, or restarted, provided sixteen 1s in a row are allowed
between management packets.)
Figure 4. MII Interface
MAC
TXD(3:0)
TXEN
TXER
TXCLK
RXCLK
RXD(3:0)
LXT98x0
RX_DV
RX_ER
CRS
COL
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