參數(shù)資料
型號: 9S12C128DGV1
英文描述: MC9S12C Family Device User Guide
中文描述: MC9S12C家庭設(shè)備用戶指南
文件頁數(shù): 110/136頁
文件大?。?/td> 2190K
代理商: 9S12C128DGV1
Device User Guide — 9S12C128DGV1/D V01.10
110
B.6.1.4 External Reset
When external reset is asserted for a time greater than PW
RSTL
the CRG module generates an internal
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.
B.6.1.5 Stop Recovery
Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR
is performed before releasing the clocks to the system.
B.6.1.6 Pseudo Stop and Wait Recovery
The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in
both modes. In Pseudo Stop Mode the voltage regulator is switched to reduced performance mode to
reducepowerconsumption.Thereturningoutofpseudostoptofullperfomancetakestvup.Thecontroller
canbewokenupbyinternalorexternalinterrupts.AftertwrsinWaitortvup+twrsinPseudoStoptheCPU
starts fetching the interrupt vector.
B.6.2 Oscillator
The device features an internal Colpitts and Pierce oscillator. The selection of Colpitts oscillator or Pierce
oscillator/external clock depends on the XCLKS signal which is sampled during reset. Pierce
oscillator/external clock mode allows the input of a square wave. Before asserting the oscillator to the
internal system clocks the quality of the oscillation is checked for each start from either power-on, STOP
oroscillatorfail.t
CQOUT
specifiesthemaximumtimebeforeswitchingtotheinternalselfclockmodeafter
POR or STOP if a proper oscillation is not detected. The quality check also determines the minimum
F
For More Information On This Product,
Go to: www.freescale.com
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