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參數(shù)資料
| 型號： | 9S12C128DGV1 |
| 英文描述： | MC9S12C Family Device User Guide |
| 中文描述： | MC9S12C家庭設備用戶指南 |
| 文件頁數(shù)： | 70/136頁 |
| 文件大?。?/td> | 2190K |
| 代理商： | 9S12C128DGV1 |
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Device User Guide — 9S12C128DGV1/D V01.10
70
changed to known start-up states. Refer to the respective module Block User Guides for register reset
states.
5.3.1 Reset Summary Table
5.3.2 Effects of Reset
When a reset occurs, MCU registers and control bits are changed to known start-up states. Refer to the
respective module Block User Guides for register reset states. Refer to the HCS12 Multiplexed External
Bus Interface (MEBI) Block Guide for mode dependent pin configuration of port A, B and E out of reset.
Refer to the PIM Block User Guide for reset configurations of all peripheral module ports.
Refer to
Figure 1-2
to
Figure 1-5
footnotes for locations of the memories depending on the operating
mode after reset.
The RAM array is not automatically initialized out of reset.
NOTE:
Fordevicesassembledin48-pinor52-pinLQFPpackagesallnon-bondedoutpins
should be configured as outputs after reset in order to avoid current drawn from
floating inputs. Refer to
Table 2-1
for affected pins.
Section 6 HCS12 Core Block Description
ConsulttheindividualblockguidesforinformationabouttheHCS12coremodules,i.e.centralprocessing
unit (CPU), interrupt module (INT), module mapping control module (MMC), multiplexed external bus
interface (MEBI), debug12 module (DBG12) and background debug mode module (BDM).
Where the CPU12 Reference Manual refers to cycles this is equivalent to device bus clock periods.
6.1 Device-specific information
6.1.1 PPAGE
External paging is not supported on these devices. In order to access the 16K flash blocks in the address
range$8000-$BFFFthePPAGEregistermustbeloadedwiththecorrespondingvalueforthisrange.Refer
to
Table 6-1
for device specific page mapping.
Table 5-2 Reset Summary
Reset
Priority
1
1
1
2
3
Source
CRG Module
RESET pin
VREG Module
CRG Module
CRG Module
Vector
Power-on Reset
External Reset
Low Voltage Reset
Clock Monitor Reset
COP Watchdog Reset
$FFFE, $FFFF
$FFFE, $FFFF
$FFFE, $FFFF
$FFFC, $FFFD
$FFFA, $FFFB
F
For More Information On This Product,
Go to: www.freescale.com
n
.
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