參數(shù)資料
型號(hào): 9S12C128DGV1
英文描述: MC9S12C Family Device User Guide
中文描述: MC9S12C家庭設(shè)備用戶指南
文件頁數(shù): 23/136頁
文件大小: 2190K
代理商: 9S12C128DGV1
23
Section 1 Introduction
1.1 Overview
The MC9S12C-Family and the MC9S12GC-Family is a 48/52/80 pin Flash-based Industrial/Automotive
network control MCU family.Members of the MC9S12C-Family and the MC9S12GC-Family deliver the
power and flexibility of our 16 Bit core (CPU12) family to a whole new range of cost and space sensitive,
general purpose Industrial and Automotive network applications. All MC9S12C-Family and
MC9S12GC-Family members are comprised of standard on-chip peripherals including a 16-bit central
processing unit (CPU12), up to 128K bytes of Flash EEPROM, up to 4K bytes of RAM, an asynchronous
serial communications interface (SCI), a serial peripheral interface (SPI), an 8-channel 16-bit timer
module (TIM), a 6-channel 8-bit Pulse Width Modulator (PWM), an 8-channel, 10-bit analog-to-digital
converter (ADC). The MC9S12C-Family members also feature a CAN 2.0 A, B software compatible
module (MSCAN12). The MC9S12C-Family as well as the MC9S12GC-Family has full 16-bit data paths
throughout. The inclusion of a PLL circuit allows power consumption and performance to be adjusted to
suit operational requirements. In addition to the I/O ports available in each module, up to 10 dedicated I/O
port bits are available with Wake-Up capability from STOP or WAIT mode. The MC9S12C-Family and
the MC9S12GC-Family devices are available in 48, 52 and 80 pin QFP packages, with the 80 Pin version
pin compatible to the HCS12 A, B and D- Family derivatives.
1.2 Features
16-bit HCS12 CORE
HCS12 CPU
i. Upward compatible with M68HC11 instruction set
ii. Interrupt stacking and programmer’s model identical to M68HC11
iii.Instruction queue
iv.Enhanced indexed addressing
MMC (memory map and interface)
INT (interrupt control)
BDM (background debug mode)
DBG12 (enhanced debug12 module, including breakpoints and change-of-flow trace buffer)
MEBI: Multiplexed Expansion Bus Interface (available only in 80 pin package version)
Wake-up interrupt inputs
Up to 12-port bits available for wake up interrupt function with digital filtering
Memory options
16K or 32KByte Flash EEPROM (erasable in 512-byte sectors)
64K, 96K or 128KByte Flash EEPROM (erasable in 1024-byte sectors)
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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