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| 型號(hào)： | 9S12C128DGV1 |
| 英文描述： | MC9S12C Family Device User Guide |
| 中文描述： | MC9S12C家庭設(shè)備用戶指南 |
| 文件頁數(shù)： | 68/136頁 |
| 文件大小： | 2190K |
| 代理商： | 9S12C128DGV1 |
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Device User Guide — 9S12C128DGV1/D V01.10
68
4.4.1 Stop
Executing the CPU STOP instruction stops all clocks and the oscillator thus putting the chip in fully static
mode. Wake up from this mode can be done via reset or external interrupts.
4.4.2 Pseudo Stop
This mode is entered by executing the CPU STOP instruction. In this mode the oscillator is still running
and the Real Time Interrupt (RTI) or Watchdog (COP) sub module can stay active. Other peripherals are
turned off. This mode consumes more current than the full STOP mode, but the wake up time from this
mode is significantly shorter.
4.4.3 Wait
This mode is entered by executing the CPU WAI instruction. In this mode the CPU will not execute
instructions.TheinternalCPUsignals(addressanddatabus)willbefullystatic.Allperipheralsstayactive.
For further power consumption reduction the peripherals can individually turn off their local clocks.
4.4.4 Run
Although this is not a low power mode, unused peripheral modules should not be enabled in order to save
power.
Section 5 Resets and Interrupts
5.1 Overview
Consult the Exception Processing section of the CPU12 Reference Manual for information.
5.2 Vectors
5.2.1 Vector Table
Table 5-1 lists interrupt sources and vectors in default order of priority.
Table 5-1 Interrupt Vector Locations
Vector Address
Interrupt Source
CCR
Mask
Local Enable
HPRIO Value
to Elevate
$FFFE, $FFFF
External Reset, Power On Reset or Low
Voltage Reset (see CRG Flags Register
to determine reset source)
Clock Monitor fail reset
COP failure reset
Unimplemented instruction trap
None
None
–
$FFFC, $FFFD
$FFFA, $FFFB
$FFF8, $FFF9
None
None
None
COPCTL (CME, FCME)
COP rate select
None
–
–
–
F
For More Information On This Product,
Go to: www.freescale.com
n
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