參數(shù)資料
型號: 9S12E128DGV1
廠商: Motorola, Inc.
英文描述: MC9S12E-Family Device User Guide V01.04
中文描述: MC9S12E -系列設(shè)備的用戶手冊V01.04
文件頁數(shù): 122/156頁
文件大?。?/td> 3077K
代理商: 9S12E128DGV1
Device User Guide — 9S12E128DGV1/D V01.04
122
B.4.1.4 External Reset
When external reset is asserted for a time greater than PW
RSTL
the CRG module generates an internal
reset, and the CPU starts fetching the reset vector without doing a clock quality check, if there was an
oscillation before reset.
B.4.1.5 Stop Recovery
Out of STOP the controller can be woken up by an external interrupt. A clock quality check as after POR
is performed before releasing the clocks to the system.
B.4.1.6 Pseudo Stop and Wait Recovery
The recovery from Pseudo STOP and Wait are essentially the same since the oscillator was not stopped in
both modes. The controller can be woken up by internal or external interrupts. After t
wrs
the CPU starts
fetching the interrupt vector.
F
For More Information On This Product,
Go to: www.freescale.com
n
.
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