參數(shù)資料
型號: 9S12E128DGV1
廠商: Motorola, Inc.
英文描述: MC9S12E-Family Device User Guide V01.04
中文描述: MC9S12E -系列設(shè)備的用戶手冊V01.04
文件頁數(shù): 124/156頁
文件大?。?/td> 3077K
代理商: 9S12E128DGV1
Device User Guide — 9S12E128DGV1/D V01.04
124
B.4.3 Phase Locked Loop
The oscillator provides the reference clock for the PLL. The PLL′s Voltage Controlled Oscillator (VCO)
is also the system clock source in self clock mode.
B.4.3.1 XFC Component Selection
This section describes the selection of the XFC components to achieve a good filter characteristics.
Figure B-2 Basic PLL functional diagram
The following procedure can be used to calculate the resistance and capacitance values using typical
values for K
1
, f
1
and i
ch
from
Table B-4
.
The grey boxes show the calculation for f
VCO
= 50MHz and f
ref
= 1MHz. E.g., these frequencies are used
for f
OSC
= 4MHz and a 25MHz bus clock.
The VCO Gain at the desired VCO frequency is approximated by:
The phase detector relationship is given by:
i
ch
is the current in tracking mode.
f
osc
1
refdv+1
f
ref
Phase
Detector
VCO
K
V
1
synr+1
f
vco
Loop Divider
K
Φ
1
2
f
cmp
C
s
R
C
p
VDDPLL
XFC Pin
K
V
K
1
e
f
K
1
1V
vco
-----------f
)
=
100
e
60
50
(
-----------------------
)
100
=
= -90.48MHz/V
K
Φ
i
ch
K
V
=
=
316.7Hz/
F
For More Information On This Product,
Go to: www.freescale.com
n
.
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