參數(shù)資料
型號： 9S12E128DGV1
廠商： Motorola, Inc.
英文描述： MC9S12E-Family Device User Guide V01.04
中文描述： MC9S12E -系列設備的用戶手冊V01.04
文件頁數(shù)： 80/156頁
文件大?。?/td> 3077K
代理商： 9S12E128DGV1
Device User Guide — 9S12E128DGV1/D V01.04
80
2.3 Detailed Signal Descriptions
2.3.1 EXTAL, XTAL — Oscillator Pins
EXTAL and XTAL are the external clock and crystal driver pins. On reset all the device clocks are derived
from the EXTAL input frequency. XTAL is the crystal output.
2.3.2 RESET — External Reset Pin
RESET is an active low bidirectional control signal that acts as an input to initialize the MCU to a known
start-up state. It also acts as an open-drain output to indicate that an internal failure has been detected in
either the clock monitor or COP watchdog circuit. External circuitry connected to the RESET pin should
not include a large capacitance that would interfere with the ability of this signal to rise to a valid logic one
within 32 ECLK cycles after the low drive is released. Upon detection of any reset, an internal circuit
drives the RESET pin low and a clocked reset sequence controls when the MCU can begin normal
processing The RESET pin includes an internal pull up device.
2.3.3 TEST — Test Pin
The TEST pin is reserved for test and must be tied to VSS in all applications.
2.3.4 XFC — PLL Loop Filter Pin
Dedicated pin used to create the PLL loop filter. See appendix
B.4.3.1
and the CRG Block Guide for more
detailed information.
2.3.5 BKGD / TAGHI / MODC — Background Debug, Tag High & Mode Pin
The BKGD / TAGHI / MODC pin is used as a pseudo-open-drain pin for the background debug
communication. It is used as a MCU operating mode select pin during reset. The state of this pin is latched
to the MODC bit at the rising edge of RESET. In MCU expanded modes of operation, when instruction
tagging is on, an input low on this pin during the falling edge of E-clock tags the high half of the instruction
word being read into the instruction queue. This pin always has an internal pull up.
2.3.6 PA[7:0] / ADDR[15:8] / DATA[15:8] — Port A I/O Pins
PA[7:0] are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus. PA[7:0] pins are not available in the 80 pin package
version.
2.3.7 PB[7:0] / ADDR[7:0] / DATA[7:0] — Port B I/O Pins
PB[7:0] are general purpose input or output pins. In MCU expanded modes of operation, these pins are
used for the multiplexed external address and data bus. PB[7:0] pins are not available in the 80 pin package
version.
F
For More Information On This Product,
Go to: www.freescale.com
n
.
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