參數(shù)資料
型號: 9S12E128DGV1
廠商: Motorola, Inc.
英文描述: MC9S12E-Family Device User Guide V01.04
中文描述: MC9S12E -系列設(shè)備的用戶手冊V01.04
文件頁數(shù): 151/156頁
文件大?。?/td> 3077K
代理商: 9S12E128DGV1
151
Table C-2 Expanded Bus Timing Characteristics (3.3V Range)
Conditions are VDDX=3.3V+/-10%, Junction Temperature -40°C to +140°C, C
LOAD
= 50pF
Num
C
Rating
Symbol
Min
Typ
Max
Unit
1
P
Frequency of operation (E-clock)
f
o
0
16.0
MHz
2
P
Cycle time
t
cyc
62.5
ns
3
D
Pulse width, E low
PW
EL
30
ns
4
D
Pulse width, E high
1
PW
EH
30
ns
5
D
Address delay time
t
AD
16
ns
6
D
Address valid time to E rise (PW
EL
–t
AD
)
t
AV
16
ns
7
D
Muxed address hold time
t
MAH
2
ns
8
D
Address hold to data valid
t
AHDS
7
ns
9
D
Data hold to address
t
DHA
2
ns
10
D
Read data setup time
t
DSR
15
ns
11
D
Read data hold time
t
DHR
0
ns
12
D
Write data delay time
t
DDW
15
ns
13
D
Write data hold time
t
DHW
2
ns
14
D
Write data setup time
(1)
(PW
EH
–t
DDW
)
t
DSW
15
ns
15
D
Address access time
(1)
(t
cyc
–t
AD
–t
DSR
)
t
ACCA
29
ns
16
D
E high access time
(1)
(PW
EH
–t
DSR
)
t
ACCE
15
ns
17
D
Non-multiplexed address delay time
t
NAD
ns
18
D
Non-muxed address valid to E rise (PW
EL
–t
NAD
)
t
NAV
ns
19
D
Non-multiplexed address hold time
t
NAH
ns
20
D
Chip select delay time
t
CSD
ns
21
D
Chip select access time
(1)
(t
cyc
–t
CSD
–t
DSR
)
t
ACCS
ns
22
D
Chip select hold time
t
CSH
ns
23
D
Chip select negated time
t
CSN
ns
24
D
Read/write delay time
t
RWD
14
ns
25
D
Read/write valid time to E rise (PW
EL
–t
RWD
)
t
RWV
16
ns
26
D
Read/write hold time
t
RWH
2
ns
27
D
Low strobe delay time
t
LSD
14
ns
28
D
Low strobe valid time to E rise (PW
EL
–t
LSD
)
t
LSV
16
ns
29
D
Low strobe hold time
t
LSH
2
ns
30
D
NOACC strobe delay time
t
NOD
14
ns
31
D
NOACC valid time to E rise (PW
EL
–t
NOD
)
t
NOV
16
ns
F
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
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