參數(shù)資料
型號(hào): 9S12E128DGV1
廠商: Motorola, Inc.
英文描述: MC9S12E-Family Device User Guide V01.04
中文描述: MC9S12E -系列設(shè)備的用戶手冊V01.04
文件頁數(shù): 134/156頁
文件大小: 3077K
代理商: 9S12E128DGV1
Device User Guide — 9S12E128DGV1/D V01.04
134
Figure B-5 SPI Master Timing (CPHA=1)
In
Table B-8
the timing characteristics for master mode are listed.
Table B-8 SPI Master Mode Timing Characteristics
Num
C
Characteristic
Symbol
Unit
Min
Typ
Max
1
/
2
1
P
SCK Frequency
f
sck
t
sck
t
lead
t
lag
t
wsck
t
su
t
hi
t
vsck
t
vss
t
ho
t
rfi
t
rfo
1/2048
f
bus
t
bus
t
sck
t
sck
t
sck
1
P
SCK Period
2
2048
2
D
Enable Lead Time
1/2
3
D
Enable Lag Time
1/2
4
D
Clock (SCK) High or Low Time
1/2
5
D
Data Setup Time (Inputs)
8
ns
6
D
Data Hold Time (Inputs)
8
ns
9
D
Data Valid after SCK Edge
30
ns
10
D
Data Valid after SS fall (CPHA=0)
15
ns
11
D
Data Hold Time (Outputs)
20
ns
12
D
Rise and Fall Time Inputs
8
ns
13
D
Rise and Fall Time Outputs
8
ns
SCK
(OUTPUT)
SCK
(OUTPUT)
MISO
(INPUT)
MOSI
(OUTPUT)
1
5
6
MSB IN
2
BIT 6 . . . 1
LSB IN
MASTER MSB OUT
2
MASTER LSB OUT
BIT 6 . . . 1
4
4
9
12
13
11
PORT DATA
(CPOL
=
0)
(CPOL
=
1)
PORT DATA
SS
1
(OUTPUT)
2
12
13
3
1.If configured as output
2. LSBF = 0. For LSBF = 1, bit order is LSB, bit 1, ..., bit 6, MSB.
F
For More Information On This Product,
Go to: www.freescale.com
n
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