- 您現(xiàn)在的位置：買(mǎi)賣(mài)IC網(wǎng) > PDF目錄4535 > A3PN250-ZVQG100 (Microsemi SoC)IC FPGA NANO 250K GATES 100-VQFP PDF資料下載
第1頁(yè)第2頁(yè)第3頁(yè)第4頁(yè)第5頁(yè)第6頁(yè)第7頁(yè)第8頁(yè)第9頁(yè)第10頁(yè)第11頁(yè)第12頁(yè)第13頁(yè)第14頁(yè)第15頁(yè)第16頁(yè)第17頁(yè)第18頁(yè)第19頁(yè)第20頁(yè)第21頁(yè)第22頁(yè)第23頁(yè)當(dāng)前第24頁(yè)第25頁(yè)第26頁(yè)第27頁(yè)第28頁(yè)第29頁(yè)第30頁(yè)第31頁(yè)第32頁(yè)第33頁(yè)第34頁(yè)第35頁(yè)第36頁(yè)第37頁(yè)第38頁(yè)第39頁(yè)第40頁(yè)第41頁(yè)第42頁(yè)第43頁(yè)第44頁(yè)第45頁(yè)第46頁(yè)第47頁(yè)第48頁(yè)第49頁(yè)第50頁(yè)第51頁(yè)第52頁(yè)第53頁(yè)第54頁(yè)第55頁(yè)第56頁(yè)第57頁(yè)第58頁(yè)第59頁(yè)第60頁(yè)第61頁(yè)第62頁(yè)第63頁(yè)第64頁(yè)第65頁(yè)第66頁(yè)第67頁(yè)第68頁(yè)第69頁(yè)第70頁(yè)第71頁(yè)第72頁(yè)第73頁(yè)第74頁(yè)第75頁(yè)第76頁(yè)第77頁(yè)第78頁(yè)第79頁(yè)第80頁(yè)第81頁(yè)第82頁(yè)第83頁(yè)第84頁(yè)第85頁(yè)第86頁(yè)第87頁(yè)第88頁(yè)第89頁(yè)第90頁(yè)第91頁(yè)第92頁(yè)第93頁(yè)第94頁(yè)第95頁(yè)第96頁(yè)第97頁(yè)第98頁(yè)第99頁(yè)第100頁(yè)第101頁(yè)第102頁(yè)第103頁(yè)第104頁(yè)第105頁(yè)第106頁(yè)第107頁(yè)第108頁(yè)第109頁(yè)第110頁(yè)第111頁(yè)第112頁(yè)第113頁(yè)第114頁(yè)
ProASIC3 nano Flash FPGAs
Revision 11
2-3
I/O Power-Up and Supply Voltage Thresholds for Power-On Reset
(Commercial and Industrial)
Sophisticated power-up management circuitry is designed into every ProASIC3 device. These circuits
ensure easy transition from the powered-off state to the powered-up state of the device. The many
different supplies can power up in any sequence with minimized current spikes or surges. In addition, the
I/O will be in a known state through the power-up sequence. The basic principle is shown in Figure 2-1
There are five regions to consider during power-up.
ProASIC3 I/Os are activated only if ALL of the following three conditions are met:
1. VCC and VCCI are above the minimum specified trip points (Figure 2-1 on page 2-4).
2. VCCI > VCC – 0.75 V (typical)
3. Chip is in the operating mode.
VCCI Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.2 V
Ramping down: 0.5 V < trip_point_down < 1.1 V
VCC Trip Point:
Ramping up: 0.6 V < trip_point_up < 1.1 V
Ramping down: 0.5 V < trip_point_down < 1 V
VCC and VCCI ramp-up trip points are about 100 mV higher than ramp-down trip points. This specifically
built-in hysteresis prevents undesirable power-up oscillations and current surges. Note the following:
During programming, I/Os become tristated and weakly pulled up to VCCI.
JTAG supply, PLL power supplies, and charge pump VPUMP supply have no influence on I/O
behavior.
PLL Behavior at Brownout Condition
Microsemi recommends using monotonic power supplies or voltage regulators to ensure proper power-
up behavior. Power ramp-up should be monotonic at least until VCC and VCCPLLX exceed brownout
activation levels. The VCC activation level is specified as 1.1 V worst-case (see Figure 2-1 on page 2-4
for more details).
When PLL power supply voltage and/or VCC levels drop below the VCC brownout levels (0.75 V ±
0.25 V), the PLL output lock signal goes low and/or the output clock is lost. Refer to the
"Power-Up/-Down Behavior of Low Power Flash Devices" chapter of the ProASIC3 nano FPGA Fabric
User’s Guide for information on clock and lock recovery.
Table 2-4 Overshoot and Undershoot Limits 1
VCCI and VMV
Average VCCI–GND Overshoot or Undershoot
Duration as a Percentage of Clock Cycle 2
Maximum Overshoot/
Undershoot 2
2.7 V or less
10%
1.4 V
5%
1.49 V
3 V
10%
1.1 V
5%
1.19 V
3.3 V
10%
0.79 V
5%
0.88 V
3.6 V
10%
0.45 V
5%
0.54 V
Notes:
1. Based on reliability requirements at 85°C.
2. The duration is allowed at one out of six clock cycles. If the overshoot/undershoot occurs at one out of two cycles, the
maximum overshoot/undershoot has to be reduced by 0.15 V.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A3PN250-ZVQ100 | IC FPGA NANO 250K GATES 100-VQFP |
| BR93L46F-WE2 | IC EEPROM 1KBIT 2MHZ 8SOP |
| AGLN030V2-ZCSG81I | IC FPGA NANO 1KB 30K 81-CSP |
| A3P125-1VQ100 | IC FPGA 1KB FLASH 125K 100-VQFP |
| A3P125-1VQG100 | IC FPGA 1KB FLASH 125K 100-VQFP |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A3PN250-ZVQG100I | 功能描述:IC FPGA NANO 250K GATES 100-VQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:ProASIC3 nano 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計(jì):- 輸入/輸出數(shù):120 門(mén)數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類(lèi)型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14） |
| A3PT5012 | 制造商:OMRON AUTOMATION AND SAFETY 功能描述:2 SPLIT SCREEN HORZ 制造商:OMRON INDUSTRIAL AUTOMATION 功能描述:Heavy Duty Switches L.P.B. |
| A3PT-5012 | 功能描述:按鈕開(kāi)關(guān) L.P.B. RoHS:否 制造商:C&K Components 觸點(diǎn)形式:2 NC - 2 NO 開(kāi)關(guān)功能:ON ? OFF 電流額定值:4 A 電壓額定值 AC:12 V to 250 V 電壓額定值 DC:12 V to 50 V 功率額定值: 安裝風(fēng)格:Through Hole 照明:Illuminated 照明顏色:None IP 等級(jí):IP 40 端接類(lèi)型:Solder 觸點(diǎn)電鍍:Silver 執(zhí)行器:Square 蓋顏色: 封裝: 可燃性等級(jí):UL 94 V-0 |
| A3PT70402 | 制造商:OMRON AUTOMATION AND SAFETY 功能描述:SWITCH UNIT 制造商:OMRON INDUSTRIAL AUTOMATION 功能描述:Switch Push Button Round Button 5A 250VAC 250VDC Alternate Contact Quick Connect/Solder Panel Mount |
| A3PT-7040-2 | 功能描述:按鈕開(kāi)關(guān) L.P.B. RoHS:否 制造商:C&K Components 觸點(diǎn)形式:2 NC - 2 NO 開(kāi)關(guān)功能:ON ? OFF 電流額定值:4 A 電壓額定值 AC:12 V to 250 V 電壓額定值 DC:12 V to 50 V 功率額定值: 安裝風(fēng)格:Through Hole 照明:Illuminated 照明顏色:None IP 等級(jí):IP 40 端接類(lèi)型:Solder 觸點(diǎn)電鍍:Silver 執(zhí)行器:Square 蓋顏色: 封裝: 可燃性等級(jí):UL 94 V-0 |
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。