2-64 Revision 11 Table 2-75 RAM512X18 Commercial-Case Conditions: T" />
參數(shù)資料
型號: A3PN250-ZVQG100
廠商: Microsemi SoC
文件頁數(shù): 91/114頁
文件大小: 0K
描述: IC FPGA NANO 250K GATES 100-VQFP
標(biāo)準(zhǔn)包裝: 90
系列: ProASIC3 nano
RAM 位總計(jì): 36864
輸入/輸出數(shù): 68
門數(shù): 250000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 100-TQFP
供應(yīng)商設(shè)備封裝: 100-VQFP(14x14)
ProASIC3 nano DC and Switching Characteristics
2-64
Revision 11
Table 2-75 RAM512X18
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
–2
–1
Std. Units
tAS
Address setup time
0.25 0.28 0.33
ns
tAH
Address hold time
0.00 0.00 0.00
ns
tENS
REN, WEN setup time
0.09 0.10 0.12
ns
tENH
REN, WEN hold time
0.06 0.07 0.08
ns
tDS
Input data (WD) setup time
0.18 0.21 0.25
ns
tDH
Input data (WD) hold time
0.00 0.00 0.00
ns
tCKQ1
Clock High to new data valid on RD (output retained)
2.16 2.46 2.89
ns
tCKQ2
Clock High to new data valid on RD (pipelined)
0.90 1.02 1.20
ns
tC2CRWH1 Address collision clk-to-clk delay for reliable read access after write on same
address; applicable to opening edge
0.50 0.43 0.38
ns
tC2CWRH1 Address collision clk-to-clk delay for reliable write access after read on same
address; applicable to opening edge
0.59 0.50 0.44
ns
tRSTBQ
RESET LOW to data out LOW on RD (flow-through)
0.92 1.05 1.23
ns
RESET LOW to data out LOW on RD (pipelined)
0.92 1.05 1.23
ns
tREMRSTB RESET removal
0.29 0.33 0.38
ns
tRECRSTB
RESET recovery
1.50 1.71 2.01
ns
tMPWRSTB RESET minimum pulse width
0.21 0.24 0.29
ns
tCYC
Clock cycle time
3.23 3.68 4.32
ns
FMAX
Maximum frequency
310
272
231 MHz
Notes:
1. For more information, refer to the application note Simultaneous Read-Write Operations in Dual-Port SRAM for Flash-
2. For specific junction temperature and voltage-supply levels, refer to Table 3-6 on page 3-4 for derating values.
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