Revision 11 2-71 JTAG 1532 Characteristics JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, " />
參數(shù)資料
型號(hào): A3PN250-ZVQG100
廠商: Microsemi SoC
文件頁數(shù): 99/114頁
文件大?。?/td> 0K
描述: IC FPGA NANO 250K GATES 100-VQFP
標(biāo)準(zhǔn)包裝: 90
系列: ProASIC3 nano
RAM 位總計(jì): 36864
輸入/輸出數(shù): 68
門數(shù): 250000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 100-TQFP
供應(yīng)商設(shè)備封裝: 100-VQFP(14x14)
ProASIC3 nano Flash FPGAs
Revision 11
2-71
JTAG 1532 Characteristics
JTAG timing delays do not include JTAG I/Os. To obtain complete JTAG timing, add I/O buffer delays to
the corresponding standard selected; refer to the I/O timing characteristics in the "User I/O
Timing Characteristics
Table 2-78 JTAG 1532
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V
Parameter
Description
–2
–1
Std.
Units
tDISU
Test Data Input Setup Time
0.53
0.60
0.71
ns
tDIHD
Test Data Input Hold Time
1.07
1.21
1.42
ns
tTMSSU
Test Mode Select Setup Time
0.53
0.60
0.71
ns
tTMDHD
Test Mode Select Hold Time
1.07
1.21
1.42
ns
tTCK2Q
Clock to Q (data out)
6.39
7.24
8.52
ns
tRSTB2Q
Reset to Q (data out)
21.31
24.15
28.41
ns
FTCKMAX
TCK Maximum Frequency
23.00
20.00
17.00
MHz
tTRSTREM
ResetB Removal Time
0.00
ns
tTRSTREC
ResetB Recovery Time
0.21
0.24
0.28
ns
tTRSTMPW
ResetB Minimum Pulse
TBD
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for
derating values.
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