2-34 Revision 11 Timing Characteristics Table 2-46 1.8 V LVCMOS Low Slew C" />
參數(shù)資料
型號(hào): A3PN250-ZVQG100
廠商: Microsemi SoC
文件頁數(shù): 58/114頁
文件大小: 0K
描述: IC FPGA NANO 250K GATES 100-VQFP
標(biāo)準(zhǔn)包裝: 90
系列: ProASIC3 nano
RAM 位總計(jì): 36864
輸入/輸出數(shù): 68
門數(shù): 250000
電源電壓: 1.425 V ~ 1.575 V
安裝類型: 表面貼裝
工作溫度: 0°C ~ 70°C
封裝/外殼: 100-TQFP
供應(yīng)商設(shè)備封裝: 100-VQFP(14x14)
ProASIC3 nano DC and Switching Characteristics
2-34
Revision 11
Timing Characteristics
Table 2-46 1.8 V LVCMOS Low Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250
Drive
Strength
Speed
Grade
tDOUT
tDP
tDIN
tPY
tPYS
tEOUT
tZL
tZH
tLZ
tHZ
Units
2 mA
Std.
0.60
15.36
0.04
1.35
1.90
0.43
13.46
15.36
2.23
1.78
ns
–1
0.51
13.07
0.04
1.15
1.61
0.36
11.45
13.07
1.90
1.51
ns
–2
0.45
11.47
0.03
1.01
1.42
0.32
10.05
11.47
1.67
1.33
ns
4 mA
Std.
0.60
10.32
0.04
1.35
1.90
0.43
9.92
10.32
2.63
2.78
ns
–1
0.51
8.78
0.04
1.15
1.61
0.36
8.44
8.78
2.23
2.37
ns
–2
0.45
7.71
0.03
1.01
1.42
0.32
7.41
7.71
1.96
2.08
ns
Note: For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
Table 2-47 1.8 V LVCMOS High Slew
Commercial-Case Conditions: TJ = 70°C, Worst-Case VCC = 1.425 V, Worst-Case VCCI = 1.7 V
Software Default Load at 35 pF for A3PN060, A3PN125, A3PN250
Drive
Strength
Speed
Grade
tDOUT
tDP
tDIN
tPY
tPYS
tEOUT
tZL
tZH
tLZ
tHZ
Units
2 mA
Std.
0.60
11.42
0.04
1.35
1.90
0.43
8.65
11.42
2.23
1.84
ns
–1
0.51
9.71
0.04
1.15
1.61
0.36
7.36
9.71
1.89
1.57
ns
–2
0.45
8.53
0.03
1.01
1.42
0.32
6.46
8.53
1.66
1.37
ns
4 mA
Std.
0.60
6.53
0.04
1.35
1.90
0.43
5.53
6.53
2.62
2.89
ns
–1
0.51
5.56
0.04
1.15
1.61
0.36
4.70
5.56
2.23
2.45
ns
–2
0.45
4.88
0.03
1.01
1.42
0.32
4.13
4.88
1.96
2.15
ns
Notes:
1. Software default selection highlighted in gray.
2. For specific junction temperature and voltage supply levels, refer to Table 2-6 on page 2-5 for derating values.
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