2-10 Revision 11 Combinatorial Cells Contribution—PC-CELL
參數(shù)資料
型號： A3PN250-ZVQG100
廠商： Microsemi SoC
文件頁數(shù)： 32/114頁
文件大?。?/td> 0K
描述： IC FPGA NANO 250K GATES 100-VQFP
標(biāo)準(zhǔn)包裝： 90
系列： ProASIC3 nano
RAM 位總計： 36864
輸入/輸出數(shù)： 68
門數(shù)： 250000
電源電壓： 1.425 V ~ 1.575 V
安裝類型： 表面貼裝
工作溫度： 0°C ~ 70°C
封裝/外殼： 100-TQFP
供應(yīng)商設(shè)備封裝： 100-VQFP（14x14）
ProASIC3 nano DC and Switching Characteristics
2-10
Revision 11
Combinatorial Cells Contribution—PC-CELL
PC-CELL = NC-CELL* 1 / 2 * PAC7 * FCLK
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-12 on page 2-11.
FCLK is the global clock signal frequency.
Routing Net Contribution—PNET
PNET = (NS-CELL + NC-CELL) * 1 / 2 * PAC8 * FCLK
NS-CELL is the number of VersaTiles used as sequential modules in the design.
NC-CELL is the number of VersaTiles used as combinatorial modules in the design.
1 is the toggle rate of VersaTile outputs—guidelines are provided in Table 2-12 on page 2-11.
FCLK is the global clock signal frequency.
I/O Input Buffer Contribution—PINPUTS
PINPUTS = NINPUTS * 2 / 2 * PAC9 * FCLK
NINPUTS is the number of I/O input buffers used in the design.
2 is the I/O buffer toggle rate—guidelines are provided in Table 2-12 on page 2-11.
FCLK is the global clock signal frequency.
I/O Output Buffer Contribution—POUTPUTS
POUTPUTS = NOUTPUTS * 2 / 2 * 1 * PAC10 * FCLK
NOUTPUTS is the number of I/O output buffers used in the design.
2 is the I/O buffer toggle rate—guidelines are provided in Table 2-12 on page 2-11.
1 is the I/O buffer enable rate—guidelines are provided in Table 2-13 on page 2-11.
FCLK is the global clock signal frequency.
RAM Contribution—PMEMORY
PMEMORY = PAC11 * NBLOCKS * FREAD-CLOCK * 2 + PAC12 * NBLOCK * FWRITE-CLOCK * 3
NBLOCKS is the number of RAM blocks used in the design.
FREAD-CLOCK is the memory read clock frequency.
2 is the RAM enable rate for read operations.
FWRITE-CLOCK is the memory write clock frequency.
3 is the RAM enable rate for write operations—guidelines are provided in Table 2-13 on page 2-11.
PLL Contribution—PPLL
PPLL = PDC4 + PAC13 * FCLKOUT
FCLKOUT is the output clock frequency.1
1.
The PLL dynamic contribution depends on the input clock frequency, the number of output clock signals generated by the
PLL, and the frequency of each output clock. If a PLL is used to generate more than one output clock, include each output
clock in the formula by adding its corresponding contribution (PAC14 * FCLKOUT product) to the total PLL contribution.
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
A3PN250-ZVQG100I 功能描述:IC FPGA NANO 250K GATES 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:ProASIC3 nano 標(biāo)準(zhǔn)包裝:152 系列:IGLOO PLUS LAB/CLB數(shù):- 邏輯元件/單元數(shù):792 RAM 位總計:- 輸入/輸出數(shù):120 門數(shù):30000 電源電壓:1.14 V ~ 1.575 V 安裝類型:表面貼裝 工作溫度:-40°C ~ 85°C 封裝/外殼:289-TFBGA，CSBGA 供應(yīng)商設(shè)備封裝:289-CSP（14x14）
A3PT5012 制造商:OMRON AUTOMATION AND SAFETY 功能描述:2 SPLIT SCREEN HORZ 制造商:OMRON INDUSTRIAL AUTOMATION 功能描述:Heavy Duty Switches L.P.B.
A3PT-5012 功能描述:按鈕開關(guān) L.P.B. RoHS:否 制造商:C&K Components 觸點形式:2 NC - 2 NO 開關(guān)功能:ON ? OFF 電流額定值:4 A 電壓額定值 AC:12 V to 250 V 電壓額定值 DC:12 V to 50 V 功率額定值: 安裝風(fēng)格:Through Hole 照明:Illuminated 照明顏色:None IP 等級:IP 40 端接類型:Solder 觸點電鍍:Silver 執(zhí)行器:Square 蓋顏色: 封裝: 可燃性等級:UL 94 V-0
A3PT70402 制造商:OMRON AUTOMATION AND SAFETY 功能描述:SWITCH UNIT 制造商:OMRON INDUSTRIAL AUTOMATION 功能描述:Switch Push Button Round Button 5A 250VAC 250VDC Alternate Contact Quick Connect/Solder Panel Mount
A3PT-7040-2 功能描述:按鈕開關(guān) L.P.B. RoHS:否 制造商:C&K Components 觸點形式:2 NC - 2 NO 開關(guān)功能:ON ? OFF 電流額定值:4 A 電壓額定值 AC:12 V to 250 V 電壓額定值 DC:12 V to 50 V 功率額定值: 安裝風(fēng)格:Through Hole 照明:Illuminated 照明顏色:None IP 等級:IP 40 端接類型:Solder 觸點電鍍:Silver 執(zhí)行器:Square 蓋顏色: 封裝: 可燃性等級:UL 94 V-0
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