參數資料
型號: A42MX16-3VQ100A
廠商: Electronic Theatre Controls, Inc.
英文描述: 40MX and 42MX FPGA Families
中文描述: 40MX和42MX FPGA系列
文件頁數: 103/120頁
文件大?。?/td> 854K
代理商: A42MX16-3VQ100A
83
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.13.5.2
The Counter2 Stage
The counter stage has three input signals (CL2, T2ICP and CLK
T1) and four output signals
(T2CAP, T2OVF, T2COM and CLK
T2). The CL2 supplies the Timer/Counter (T2CNT) with
clocks and the T2ICP signal or CLK
T1 signal capture the counter value in the capture register.
The CLK
T2 is the output clock and T2CAP, T2OVF, and T2COMP are the interrupt request sig-
nals of the counter stage.
Figure 3-30. 16-bit Counter Stage
Signal description of the Timer/counter2 (internal signals):
CL2
Timer/counter input clock
CLK
T1
Timer1 output clock
T2ICP
Timer2 input capture signal
T2CAP
Timer/counter capture event interrupt
T2OVF
Timer/counter counter overflow interrupt
T2COM
Timer/counter compare match interrupt
CLK
T2
Timer/counter stage output clock
CMR
Timer/counter compare register match
CMF
Timer/counter compare fixed TOP match
CPR
Timer/counter reset for capture event
RES
Timer/counter reset (clear all bits)
OVF
Timer/counter overflow
T2CPE
Timer/counter capture signal
CLKT1
T2CNT
T2ICP
CL2
T2OVF
T2CAP
T2COMP
CLKT2
T2COR
T2ICR
Timer/Counter
Control
T2CPIM
T2OTM
T2OIM
T2CPRM
T2CTM
T2CIM
T2CRM
T2TP1..0
CPR
T2CPE
CP
OVF
CMR
CMF
RES
= 0x00FF
Fixed TOP values
= 0x01FF
Disable
= 0x03FF
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