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| 型號(hào)： | A42MX16-3VQ100A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁(yè)數(shù)： | 78/120頁(yè) |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX16-3VQ100A |
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60
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
WRx, WPx, WDx, RRx, RPx, and RDx are common to all pins within the same port. CLK
I/O,
SLEEP, and PUD are common to all ports. All other signals are unique for each pin.
Table 3-21, summarizes the function of the overriding signals. The pin and port indexes are not
shown in the succeeding tables. The overriding signals are generated internally in the modules
having the alternate function.
The following subsections shortly describe the alternate functions for each port, and relate the
overriding signals to the alternate function. Refer to the alternate function description for further
details.
Table 3-21.
Generic Description of Overriding Signals for Alternate Functions
Signal
Name
Full Name
Description
PUOE
Pull-up Override
Enable
If this signal is set, the pull-up enable is controlled by the PUOV
signal. If this signal is cleared, the pull-up is enabled when
{DDxn, PORTxn, PUD} = 0b010.
PUOV
Pull-up Override Value
If PUOE is set, the pull-up is enabled/disabled when PUOV is
set/cleared, regardless of the setting of the DDxn, PORTxn, and PUD
Register bits.
DDOE
Data Direction
Override Enable
If this signal is set, the Output Driver Enable is controlled by the
DDOV signal. If this signal is cleared, the Output driver is enabled by
the DDxn Register bit.
DDOV
Data Direction
Override Value
If DDOE is set, the Output Driver is enabled/disabled when DDOV is
set/cleared, regardless of the setting of the DDxn Register bit.
PVOE
Port Value Override
Enable
If this signal is set and the Output Driver is enabled, the port value is
controlled by the PVOV signal. If PVOE is cleared, and the Output
Driver is enabled, the port Value is controlled by the PORTxn
Register bit.
PVOV
Port Value Override
Value
If PVOE is set, the port value is set to PVOV, regardless of the setting
of the PORTxn Register bit.
PTOE
Port Toggle Override
Enable
If PTOE is set, the PORTxn Register bit is inverted.
DIEOE
Digital Input Enable
Override Enable
If this bit is set, the Digital Input Enable is controlled by the DIEOV
signal. If this signal is cleared, the Digital Input Enable is determined
by MCU state (Normal mode, sleep mode).
DIEOV
Digital Input Enable
Override Value
If DIEOE is set, the Digital Input is enabled/disabled when DIEOV is
set/cleared, regardless of the MCU state (Normal mode, sleep
mode).
DI
Digital Input
This is the Digital Input to alternate functions. In the figure, the signal
is connected to the output of the schmitt-trigger but before the
synchronizer. Unless the Digital Input is used as a clock source, the
module with the alternate function will use its own synchronizer.
AIO
Analog
Input/Output
This is the Analog Input/output to/from alternate functions. The signal
is connected directly to the pad, and can be used bi-directionally.
相關(guān)PDF資料 |
PDF描述 |
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| A42MX16-3VQ100B | 40MX and 42MX FPGA Families |
| A42MX24-2PQ100B | 40MX and 42MX FPGA Families |
| A42MX24-2PQ100ES | 40MX and 42MX FPGA Families |
| A42MX24-2TQ100 | 40MX and 42MX FPGA Families |
| A42MX24-2TQ100A | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-3VQ100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3VQ100ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3VQ100I | 功能描述:IC FPGA MX SGL CHIP 24K 100-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
| A42MX16-3VQ100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3VQG100 | 功能描述:IC FPGA MX SGL CHIP 24K 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
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