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| 型號(hào)： | A42MX16-3VQ100A |
| 廠(chǎng)商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁(yè)數(shù)： | 47/120頁(yè) |
| 文件大小： | 854K |
| 代理商： | A42MX16-3VQ100A |
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32
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.7.2
Clock Systems and their Distribution
Figure 3-13 presents the principal clock systems in the Atmel
AVR and their distribution. All of
the clocks need not be active at a given time. In order to reduce power consumption, the clocks
to modules not being used can be halted by using different sleep modes, as described in Section
3.8 “Power Management and Sleep Modes” on page 38. The clock systems are described in
detail below.
Figure 3-13. Clock Distribution
System Clock Prescaler Output - CLK
The system clock prescaler output signal (CLK) is used as clock sources for microcontroller, and
it will affect the clock frequency of the CPU and all synchronous peripherals. CLK
I/O, CLKCPU,
and CLK
Flash are divided by a factor as shown in Table 3-10 on page 37.
CPU Clock - CLK
CPU
The CPU clock is routed to parts of the system concerned with operation of the Atmel AVR core.
Examples of such modules are the General Purpose Register File, the Status Register and the
data memory holding the Stack Pointer. Halting the CPU clock inhibits the core from performing
general operations and calculations.
I/O Clock - CLK
I/O
The I/O clock is used by the majority of the I/O modules, like Timer/Counters, SPI, and Ports.
The I/O clock is also used by the External Interrupt module, but note that some external inter-
rupts are detected by asynchronous logic, allowing such interrupts to be detected even if the I/O
clock is halted.
Flash Clock - CLK
FLASH
The Flash clock controls operation of the Flash interface. The Flash clock is usually active simul-
taneously with the CPU clock.
Timer Clock Prescaler Output - CLT
The Timer clock allows the asynchronous Timer3/Counter3 to be clocked with a faster clock as
the I/O Clock (CLK
I/O). The Timer clock is usually active simultaneously with the CPU clock.
CLKI/O
Calibrated FRC
Oscillator
Calibrated SRC
Oscillator
System Prescaler
Reset Logic
Timer Clock
Prescaler
Multiplexer
General I/O
Modules
LF-Receiver
CPU Core
AVR Clock Module Unit
RAM
FRC
Timer/Counter
Flash and
EEPROM
CLT
SRC
CLKI/O
CLKFlash
CLKCPU
CLT
SCl
SCH
CLK
ECL
FRC
CL
SRC
External Clocks
SCH
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX16-3VQ100B | 40MX and 42MX FPGA Families |
| A42MX24-2PQ100B | 40MX and 42MX FPGA Families |
| A42MX24-2PQ100ES | 40MX and 42MX FPGA Families |
| A42MX24-2TQ100 | 40MX and 42MX FPGA Families |
| A42MX24-2TQ100A | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-3VQ100B | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3VQ100ES | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3VQ100I | 功能描述:IC FPGA MX SGL CHIP 24K 100-VQFP RoHS:否 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門(mén)數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類(lèi)型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
| A42MX16-3VQ100M | 制造商:未知廠(chǎng)家 制造商全稱(chēng):未知廠(chǎng)家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3VQG100 | 功能描述:IC FPGA MX SGL CHIP 24K 100-VQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門(mén)陣列） 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門(mén)數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類(lèi)型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
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