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參數(shù)資料
| 型號： | A42MX16-3VQ100A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁數(shù)： | 83/120頁 |
| 文件大小： | 854K |
| 代理商： | A42MX16-3VQ100A |
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65
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
The alternate pin configuration on Port D:
SDIN/PCINT23 - Port D, Bit 7
SDIN: Serial Data Input. External serial data input of the SSI on PD7 pin. When in the Timer2
modulator the SPI mode of the SSI is selected (T2M[3..0] = 0b1001), this pin is configured as an
input regardless of the setting of DDD7. When the pin is forced to be an input, the pull-up can
still be controlled by the PORTD7 bit.
PCINT23, Pin Change Interrupt Source 23: The PD7 pin can serve as an external interrupt
source.
T2O2/PCINT22 - Port D, Bit 6
T2O2: Timer2 Output 2. The PD6 pin can serve as an external out for the Timer2 modulator out-
put 2. The function of the modulator output pin is depend on the Timer2 Mode bits T2M[3..0] bits
in the T2MRB register. The PD6 pin has to be configured as an output (DDD6 set [one]) if the
timer mode is used the output pin to serve this function. When PD6 is not used as modulator out-
put pin, it is a I/O pin.
PCINT22, Pin Change Interrupt Source 22: The PD6 pin can serve as an external interrupt
source.
T2O1/PCINT21 - Port D, Bit 5
T2O1: Timer2 Output 1. The PD5 pin can serve as an external out for the Timer2 modulator out-
put 1. The function of the modulator output pin is depend on the Timer2 Mode bits T2M[3..0] bits
in the T2MRB register. The PD5 pin has to be configured as an output (DDD5 set [one]) if the
timer mode is used the output pin to serve this function. When PD5 is not used as modulator out-
put pin, it is a I/O pin.
PCINT21, Pin Change Interrupt Source 21: The PD5 pin can serve as an external interrupt
source.
ECIN1/PCINT20 - Port D, Bit 4
ECIN1: External Clock Input. External system clock input for the clock module on PD4 pin. When
used as a clock pin, the pin can not be used as an I/O pin. The clock will be input if the
CMM[1..0] bits are set (one), the ECINS bit is set (one) and CCS bit is set (one) in the CMCR
register, regardless of the PORTD4 and DDD4 setting, and PORTD4, DDD4 and PIND4 will all
read 0.
PCINT20, Pin Change Interrupt Source 20: The PD4 pin can serve as an external interrupt
source.
INT1/PCINT19 - Port D, Bit 3
INT1: External Interrupt source 1. The PD3 pin can serve as an external interrupt source.
The pin has to be configured as an input (DDD3 set (zero)) to serve this function.
PCINT19, Pin Change Interrupt Source 19: The PD3 pin can serve as an external interrupt
source.
INT0/PCINT18 - Port D, Bit 2
INT0: External Interrupt source 1. The PD2 pin can serve as an external interrupt source.
The pin has to be configured as an input (DDD2 set (zero)) to serve this function.
PCINT18, Pin Change Interrupt Source 18: The PD2 pin can serve as an external interrupt
source.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX16-3VQ100B | 40MX and 42MX FPGA Families |
| A42MX24-2PQ100B | 40MX and 42MX FPGA Families |
| A42MX24-2PQ100ES | 40MX and 42MX FPGA Families |
| A42MX24-2TQ100 | 40MX and 42MX FPGA Families |
| A42MX24-2TQ100A | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-3VQ100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3VQ100ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3VQ100I | 功能描述:IC FPGA MX SGL CHIP 24K 100-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
| A42MX16-3VQ100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3VQG100 | 功能描述:IC FPGA MX SGL CHIP 24K 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計:- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
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