參數(shù)資料
型號: A42MX16-3VQ100A
廠商: Electronic Theatre Controls, Inc.
英文描述: 40MX and 42MX FPGA Families
中文描述: 40MX和42MX FPGA系列
文件頁數(shù): 62/120頁
文件大?。?/td> 854K
代理商: A42MX16-3VQ100A
46
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
3.9.2.6
MCU Status Register - MCUSR
The MCU Status Register provides information on which reset source caused an MCU reset
Bits 7, 6, 4 - Res: Reserved Bits
These bits are reserved bits at the ATA6289 and will always read as zero.
Bit 5 - TSRF: Temperature Shutdown Reset Flag
This bit is set, if the ambient temperature exceeds the specified threshold temperature (T
SD) and
temperature shutdown mode is enabled by the TSSD Bit in the TSCR register. This bit will be
reset by a Power-on Reset, or by writing a logic zero to the flag.
Bit 3 - WDRF: Watchdog Reset Flag
This bit is set if a Watchdog Reset occurs and Watchdog is enabled. The bit is reset by a
Power-on Reset, or by writing a logic zero to the flag.
Bit 2 - BORF: Brown-Out Reset Flag
This bit is set if a Brown-out Reset occurs and BOD is enabled. The bit is reset by a Power-on
Reset, or by writing a logic zero to the flag.
Bit 1 - EXTRF: EXTernal Reset Flag
This bit is set if an External Reset occurs. The bit is reset by a Power-on Reset, or by writing a
logic zero to the flag.
Bit 0 - PORF: Power-On Reset Flag
This bit is set if a Power-on Reset occurs. The bit is reset only by writing a logic zero to the flag.
To make use of the Reset Flags to identify a reset condition, the user should read and then reset
the MCUSR as early as possible in the program. If the register is cleared before another reset
occurs, the source of the reset can be found by examining the Reset Flags.
Bit
7
654
32
10
-
TSRF
-
WDRF
BORF
EXTRF
PORF
MCUSR
Read/Write
R
R/W
R
R/W
Initial Value
0
000
00
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