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| 型號(hào)： | A42MX16-3VQ100A |
| 廠商： | Electronic Theatre Controls, Inc. |
| 英文描述： | 40MX and 42MX FPGA Families |
| 中文描述： | 40MX和42MX FPGA系列 |
| 文件頁(yè)數(shù)： | 18/120頁(yè) |
| 文件大?。?/td> | 854K |
| 代理商： | A42MX16-3VQ100A |
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114
4958B–AUTO–11/10
Atmel ATA6285/ATA6286 [Preliminary]
When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and pin is overridden
according Table 3-46. For more details on automatic port overrides, refer to Section 3.12.3
3.14.1
SS - Pin Functionality
3.14.1.1
Slave Mode
When the SPI is configured as a Slave, the Slave Select SS - pin is always input. When SS is
held low, the SPI is activated, and MISO becomes an output if configured by the user. All other
pins are inputs. When SS is driven high, all pins are inputs, and the SPI is passive, which means
that it will not receive incoming data. Note that the SPI logic will be reset once the SS pin is
driven high.
The SS - pin is useful for packet/byte synchronization to keep the slave bit counter synchronous
with the master clock generator. When the SS - pin is driven high, the SPI slave will immediately
reset the send and receive logic, and drop any partially received data in the Shift Register.
3.14.1.2
Master Mode
When the SPI is configured as a Master (MSTR in SPCR is set), the user can determine the
direction of the SS - pin.
If SS is configured as an output, the pin is a general output pin which does not affect the SPI
system. Typically, the pin will be driving the SS - pin of the SPI Slave.
If SS is configured as an input, it must be held high to ensure Master SPI operation. If the
SS - pin is driven low by peripheral circuitry when the SPI is configured as a Master with the
SS - pin defined as an input, the SPI system interprets this as another master, selecting the SPI
as a slave and starting to send data to it. To avoid bus contention, the SPI system takes the fol-
lowing actions:
The MSTR bit in SPCR is cleared and the SPI system becomes a Slave. As a result of the SPI
becoming a Slave, the MOSI and SCK pins become inputs.
The SPIF Flag in SPSR is set, and if the SPI interrupt is enabled, and the I-bit in SREG is set,
the interrupt routine will be executed.
Thus, when interrupt-driven SPI transmission is used in Master mode, and there exists a possi-
bility that SS is driven low, the interrupt should always check that the MSTR bit is still set. If the
MSTR bit has been cleared by a slave select, it must be set by the user to re-enable SPI Master
mode.
Table 3-46.
SPI Pin Overrides
Pin
Direction, Master SPI
Direction, Slave SPI
MOSI
User Defined
Input
MISO
Input
User Defined
SCK
User Defined
Input
SS
User Defined
Input
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| A42MX16-3VQ100B | 40MX and 42MX FPGA Families |
| A42MX24-2PQ100B | 40MX and 42MX FPGA Families |
| A42MX24-2PQ100ES | 40MX and 42MX FPGA Families |
| A42MX24-2TQ100 | 40MX and 42MX FPGA Families |
| A42MX24-2TQ100A | 40MX and 42MX FPGA Families |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| A42MX16-3VQ100B | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3VQ100ES | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3VQ100I | 功能描述:IC FPGA MX SGL CHIP 24K 100-VQFP RoHS:否 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
| A42MX16-3VQ100M | 制造商:未知廠家 制造商全稱:未知廠家 功能描述:40MX and 42MX FPGA Families |
| A42MX16-3VQG100 | 功能描述:IC FPGA MX SGL CHIP 24K 100-VQFP RoHS:是 類別:集成電路 (IC) >> 嵌入式 - FPGA（現(xiàn)場(chǎng)可編程門陣列） 系列:MX 標(biāo)準(zhǔn)包裝:40 系列:SX-A LAB/CLB數(shù):6036 邏輯元件/單元數(shù):- RAM 位總計(jì):- 輸入/輸出數(shù):360 門數(shù):108000 電源電壓:2.25 V ~ 5.25 V 安裝類型:表面貼裝 工作溫度:0°C ~ 70°C 封裝/外殼:484-BGA 供應(yīng)商設(shè)備封裝:484-FPBGA（27X27） |
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