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參數(shù)資料
| 型號(hào)： | AD6636BC |
| 廠商： | Analog Devices, Inc. |
| 元件分類： | 數(shù)字上／下變頻 |
| 英文描述： | 150 MSPS Wideband Digital Down-Converter (DDC) |
| 中文描述： | 150MSPS的寬帶數(shù)字下變頻器（DDC） |
| 文件頁數(shù)： | 22/72頁 |
| 文件大?。?/td> | 1629K |
| 代理商： | AD6636BC |
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AD6636
delay given by the 6-bit value (maximum delay of 63 clock
cycles) is placed between the gain control output and the
EXP[2:0] input. Therefore, the external gain-ranging block’s
settling delays are compensated for in the AD6636.
Rev. 0 | Page 22 of 72
Note that any gain changes that are initiated during the
relinearization period are ignored. For example, if the AD6636
detects that a gain adjustment is required during the relineariza-
tion period of a previous gain adjustment, then the new
adjustment is ignored.
Setting Up the Gain Control Block
To set up the gain control block for individual input ports, the
individual upper threshold registers and lower threshold
registers should be written with appropriate values. The 10-bit
values written into upper and lower threshold registers are
compared to the 10 MSB bits of the absolute magnitude
calculated using the input port data. The 20-bit dwell timer
register should have the appropriate number of clock cycles to
provide temporal hysteresis.
A 6-bit relinearization pipeline delay word is set to synchronize
with the settling delay in the external gain ranging circuitry.
Finally, the gain control enable bit is written with Logic 1 to
activate the gain control block. On enabling, the gain control
output bits are made 000 (output on EXP[2:0] pins), which
represent the minimum gain for the external gain-ranging
circuitry and corresponding minimum attenuation during
relinearization. The normal functioning takes over, as explained
previously in this section.
Complex Inputs
For complex inputs (formed by pairing two input ports), only
one set of EXP[2:0] pins should be used as the gain control
output. For the pair of Input Ports A and B, gain control
circuitry for Input Port A is active, and EXPA[2:0] should be
connected externally as the gain control output. The gain
control circuitry for Input Port B is not activated (shut down),
and EXPB[2:0] is forced to be equal to EXP[2:0].
0
DWELL
TIMER
COMPARE
A < B
INC
DEC
EXP GEN
FROM
MEMORY
MAP
EXP [2:0]
A
B
LOWER
THRESHOLD
REGISTER
COMPARE
A > B
FROM
MEMORY
MAP
B
A
LOWER
THRESHOLD
REGISTER
FROM INPUT
PORTS
INCREASE
EXTERNAL GAIN
DECREASE
EXTERNAL GAIN
Figure 25. AD6636 Gain Control Block Diagram
ADC INPUT PORT MONITOR FUNCTION
The AD6636 provides a power-monitor function that can
monitor and gather statistics about the received signal in a
signal chain. Each input port is equipped with an individual
power-monitor function that can operate both in real and in
complex modes of the input port. This function block can
operate in one of three modes, which measure the following
over a programmable period of time:
Peak power
Mean power
Number of samples crossing a threshold
These functions are controlled via the 2-bit power-monitor
function select bits of the power monitor control register for
each individual input port. The input ports can be set for
different modes, but only one function can be active at a time
for any given input port.
The three modes of operation can function continuously over a
programmable time period. This time period is programmed as
the number of input clock cycles in a 24-bit ADC monitor
period register (AMPR). This register is separate for each input
port. An internal magnitude storage register (MSR) is used to
monitor, accumulate, or count, depending on the mode of
operation.
Peak Detector Mode (Control Bits 00)
The magnitude of the input port signal is monitored over a
programmable time period (given by AMPR) to give the peak
value detected. This mode is set by programming Logic 0 in the
power-monitor function select bits of the power-monitor
control register for each individual input port. The 24-bit
AMPR must be programmed before activating this mode.
After enabling this mode, the value in the AMPR is loaded into
a monitor period timer and the countdown is started. The
magnitude of the input signal is compared to the MSR, and the
greater of the two is updated back into the MSR. The initial
value of the MSR is set to the current ADC input signal
magnitude. This comparison continues until the monitor period
timer reaches a count of 1.
When the monitor period timer reaches a count of 1, the value
in the MSR is transferred to the power-monitor holding register,
which can be read through the microport or the serial port. The
monitor period timer is reloaded with the value in the AMPR,
and the countdown is started. Also, the first input sample’s
magnitude is updated in the MSR, and the comparison and
update procedure, as explained above, continues. If the interrupt
is enabled, an interrupt is generated, and the interrupt status
register is updated when the AMPR reaches a count of 1.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD6636BC/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For 150MSPS Wideband Digital Down-Converter 制造商:Analog Devices 功能描述:EVALUATION BOARD AD6636 - Bulk |
| AD6636BC/PCBZ | 制造商:Analog Devices 功能描述:Evaluation Kit For 150 MSPS, Wide Band, Digital Down Converter 制造商:Analog Devices 功能描述:EVALUATION BOARD AD6636 - Bulk |
| AD6636CBC | 制造商:Rochester Electronics LLC 功能描述: 制造商:Analog Devices 功能描述: |
| AD6636CBCZ | 功能描述:IC DIGITAL DWNCONV 4CH 256CSPBGA RoHS:是 類別:RF/IF 和 RFID >> RF 混頻器 系列:AD6636 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:100 系列:- RF 型:W-CDMA 頻率:2.11GHz ~ 2.17GHz 混頻器數(shù)目:1 增益:17dB 噪音數(shù)據(jù):2.2dB 次要屬性:- 電流 - 電源:11.7mA 電源電壓:2.7 V ~ 3.3 V 包裝:托盤 封裝/外殼:12-VFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:12-QFN-EP（3x3） |
| AD6636CBCZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:150 MSPS Wideband Digital Down-Converter (DDC) |
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